Don’t combine memory kits! The meat and potatoes overview Spurred by the abundance of combined memory kit related issue threads in the forums, we've put together a quick discourse for you today. Have fun - and don't mind my "humor"!
Pricing of memory kits can make it attractive for users to fill all available memory slots with modules even if their usage scenario does not require a lot of memory capacity. Often, users will take the most cost-attractive solution to do this – buying multiple memory kits, whether of the same model or in some cases dissimilar models and then expect the memory kits to work plug-and-play when used in tandem. There are several reasons why this is a bad idea:
- Memory vendors bin memory kits at their rated density. If an end-user combines memory kits to make up a higher density, the memory timings that each kit is programmed with are no longer valid or guaranteed to work. In fact, memory vendors themselves advise users not to combine kits.
There are numerous technical reasons for this – some of which require a deep understanding of electronics and memory systems. Most of us are not equipped to understand the technical reasons of why combining memory kits can cause issues. We’ll provide some information in this guide that may help, although we cannot cover some of the advanced topics at an elementary level as there is no way to dumb the information down easily or accurately.
- If the rated timings of a single kit don’t work when memory kits are combined, the end-user will often need to return both memory kits to the point of sale and purchase a single memory kit, or one needs to tune the system to try and get both memory kits stable. This can be difficult, as again, it requires a level of understanding and acceptance that the rated timings and frequency of a single kit, may not be achieved when running two or more memory kits together.
A teenie-weenie snapshot of COMBINED memory kit issues
- Tuning memory related settings and voltages takes a lot of time, a systematic approach and obviously patience. If one has little or no knowledge of what memory timings mean or do, then getting through the process and having a full head of hair at the end of it, is nigh-on impossible. That’s why we recommend users do not combine memory kits! No, we’re not saving the world from stress related male baldness or deliberating over the attractiveness of egg-headed bald women – we’re saving you time and stress. Purchasing a single memory kit makes things easier on the system and the end-user.
I may at a future date add a picture to this section - however, requirements for the guide in current form trump available time so it is text only for now.
This is where things get tricky. How to describe advanced things in a basic form that most can relate to? Hmm... To hell with it! You’ll either get it or you won’t ! 😛
To access system memory, the memory controller (within the processor on modern architectures), sends signals to the memory modules via certain memory traces on the board. The layout of these traces is carefully designed by motherboard engineers to avoid electrical issues such as cross talk, timing mismatch between signal lines and ringing. Enthusiast motherboards have more PCB layers to help minimize these issues and on such motherboards, more work goes into eliminating obstacles to maximize platform overclocking range. Don’t worry if we’ve lost you a bit here – it’s not a requirement for you to understand the section above. However, it is good for one to recognise that there are plenty of things beyond our current level of understanding when it comes to building PCs – yes even if you’re the type of user that proclaims 20 years of PC building experience as some kind of superlative, unconditional qualification. Hopefully, accepting that these things are beyond one’s level of understanding, serves as a deterrent to combining memory kits.
I’d love to stop right here and wrap this up, but I know you 20 years of experience PC builders “aren’t going to be fooled by that” . Yes, yes, I know, you can smell marketing BS a mile off can’t you? After all, you’ve been building PCs for 20 years and know what a memory module looks like and you know how to put it into the memory slot the right way.
Getting back to the topic, every transaction between the processor’s memory controller and memory modules requires some form of timing alignment and some time spacing to ensure that the electrical value of a signal does not become corrupt as it is transferred, read or written to/from the memory modules. The value of signals in computer systems is either high, low (binary 1 and 0) or off. When system memory is unstable, a logic low (0) may be seen as a 1, or off state may register as a 0. This can cause applications to freeze, the operating system to crash, or prevent the system from POSTIng because it fails POST stress tests. In context of the subject we're dealing with in this guide, memory stability is related directly to two things: system voltages and memory timings.
The numerical value for most memory timings in UEFI denotes a time based delay in DRAM memory clock cycles. Each memory timing sets the delay for a particular operation or between a transaction and the subsequent operation. The minimum theoretical delay for most of these timings is dictated by memory architecture – many read to read related memory timings, or write to write timings have a minimum internal value of 4 DRAM clocks. Not all do, for example, some are bound by a 6 clock minimum on DDR4. There are other types of timings too, but for sake of brevity in this “guide”, we’ll stick with these two crude examples as a primer.
Indeed, setting the lowest possible value for these timings (where available), results in faster memory performance, however, the lowest value may not be unconditionally stable and may give rise to the memory instability we discussed above. When a memory vendor releases a memory kit, they do so after evaluating stability thoroughly. During the evaluation phase, the memory vendor will test different memory IC types and apply timing offsets the memory ICs (and later) modules can handle at a given voltage and frequency – this is usually dictated by memory IC type and the platform the IC has been developed for. Unless it's a premium memory kit, chances are the memory modules and the platform itself is not capable of running the minimum possible value for each memory timing. Moreover, there are additional concessions that need to be accounted for when dealing with different memory densities.
In almost all cases, when using more ICs (more memory modules), or higher density ICs from the same family, additional timing delays need to be applied for the system to remain stable. Reasons abound, the more ICs or modules the processor’s memory controller has to deal with, the less stability margin the system will have. This results in the need for larger timing delays to ensure platform stability.
Memory kits are programmed with the timings and frequency that the memory vendor found to be stable for a given density - a single memory kit in other words. If a 16GB kit can handle a particular memory timing at 10 clocks, that’s what the memory vendor will program into the memory kit’s XMP or SPD profile. If we add another 16GB of the same kit to the system, it’s probable that this 10 clock delay needs to be increased to 12 or more clocks in order to ensure stability. It could be worse still – the modules may require more voltage or not be capable of running at a given frequency at all. Either way, the system will only have the timings of a single memory kit to reference, leaving any adjustments to the end-user to perform. There’s the primary cause for end-user frustration right there – most are not equipped to deal with the situation and end up frustrated, blaming all and sundry for their misadventure.
So please do yourself a favor – do not combine memory kits. Purchase a single memory kit at the rated density and timings that you need. Perform research, ask questions then buy. Don’t do it backwards J