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X670 / X870 resource thread

Shamino
Moderator

ill use this thread to collect some new test bioses for the boards, maybe also to explain some less understood options

to disable cores ccd go here and choose ccd xx bit map down core.
each ones stand for an enabled core
best to disable from the back, ie:
110000
instead of 0011000
after selection press downcore apply changes or discard if made mistake

ocpak/octools

FAQ:
7950x not boosting pass 5.5G -> check that CStates is not disabled
Detailed Explanation on CState Boot Limiter


Test BIOSes:

new:
X3D OC Preset for those MB with asynch BCLK Support: (for simple slight perf boost for X3D)
97792

DOCP/EXPO Tweaked: (for simple timings tightening)
97793

strixe-e 1515 

strixe-f 1515 

strix e a 1515 

crosshair hero 1515 

crosshair gene 1515 

crosshair extreme 1515 

creator 670 1515

creator b650 1515

strix 650E I

strix 670 itx

 

 

for crosshair and strix e-e:

explanation of segment2 Loadline:

dualseg.jpg

customize a heterogenous loadline for a dual segment workload range.

example above shows loadline=L6 when current is in range of 0~40A, and Level4 when current is above 40A.

 

 

 


Adds for x3d

dynamic ccd priority switch with core flex, os / driver agnostic so win10 win11 ok

97403

97404

Algo as follows:
If condition reached and ccd0 specified, then check current mem/cache activity > threshold and hysteresis reached, if fulfilled then switch
If condition reached and ccd1 specified, then check current mem/cache activity <=threshold and hysteresis reached,, if fulfilled then switch
Default hysteresis =4

Can combine multiple algos for ccd priority so combinations are wide

works on non x3d too but of course senseless on it. detailed explanation here.

10,891 Views
3,183 REPLIES 3,183

ksenchy
Level 11

Does this new version already have AGESA 1.2.0.2?

Zheega
Level 10

No, it is 1.2.0.1a.

SAFEDISK
Level 11

105w.jpg

ROG STRIX/TUF/PROART B650 Series Beta Bios 3034

1) Add cTDP to 105W item for 9600X/9700X

dont use older cmo file

ROG STRIX B650-A GAMING WIFI Beta Bios 3034
https://drive.google.com/file/d/1VLVfF6yRgn4Ls7oPpeUdStFbh9Fz6Qlm/view?usp=sharing

ROG STRIX B650E-E GAMING WIFI Beta Bios 3034
https://drive.google.com/file/d/1B7YH2LyCm_u167t8EzPPEX--ZEUoyJCQ/view?usp=sharing

ROG STRIX B650E-F GAMING WIFI Beta Bios 3034
https://drive.google.com/file/d/1M2GYq6bxMbAw5D7-ySx3G6ASTOwiDUs5/view?usp=sharing

ROG STRIX B650E-I GAMING WIFI Beta Bios 3034
https://drive.google.com/file/d/1dlsQ0cVMlq2znXFVqmUnK4cqGZOPMwfL/view?usp=sharing


TUF GAMING B650-E WIFI Beta Bios 3034
https://drive.google.com/file/d/1QkwolRQCMhekBlSQ4FciLXakZcBSmmjd/view?usp=sharing

TUF GAMING B650-PLUS Beta Bios 3034
https://drive.google.com/file/d/1RHGEpcuiDEcj7OQdE1ZUbrkV-I9YY-EB/view?usp=sharing

TUF GAMING B650-PLUS WIFI Beta Bios 3034
https://drive.google.com/file/d/1MW-AHIF5fudtQvjMMjuXU7xSGT4l7FDN/view?usp=sharing

TUF GAMING B650M-E Beta Bios 3034
https://drive.google.com/file/d/1NvqHoPejVbe2i15r9AcYs1nBjX9_QGe-/view?usp=sharing

TUF GAMING B650M-E WIFI Beta Bios 3034
https://drive.google.com/file/d/1Ei2rzSUFbCUsHTGdsIXnOWs_HEaeWZYt/view?usp=sharing

TUF GAMING B650M-PLUS Beta Bios 3034
https://drive.google.com/file/d/1WdJySt_yP2ewAPO9L3U4AehtyeyaZiQb/view?usp=sharing

TUF GAMING B650M-PLUS WIFI Beta Bios 3034
https://drive.google.com/file/d/1CFe4uMWOM3dUxuNa5WFtDkgr8acyqnyP/view?usp=sharing


PROART B650-CREATOR Beta Bios 2307
https://drive.google.com/file/d/1wXd7N6oxrU3pkAkG8mQQGksFpkIrt9Go/view?usp=sharing

my tests returned with a lot of instability in the memories, even trying to reset some parameters. Now I can't say if the voltage training option is to blame, because I activated it in the previous beta and there was no problem. Curve shaper can lock the bios, this time I started by leaving it disabled, then I activated it and set the curve shaper values, but when I tried to change the settings again, it crashed, so I had to keep it turned off.

I'm not even going to use the machine until a new batch comes out.

I wrote down the sequence of some configurations and attempts to modify the impedances:

Ai Overclock Tuner [Auto]
Memory Frequency [DDR5-6200MHz]
FCLK Frequency [2167 MHz]
Core Performance Boost [Enabled]
CPU Core Ratio [CPU Core Ratio]
CPU Core Ratio [48.50]
Core VID [Auto]
CCX0 Ratio [52.00]
CCX0 Ratio [52.50]
Dynamic OC Switcher [Enabled]
Current Threshold to Switch to OC Mode [60]
Calibrated Temperature Threshold to switch back [80]
Hysteresis [0]
GPU Boost [Auto]
Tcl [30]
Trcd [36]
Trp [32]
Tras [36]
Trc [38]
Twr [48]
Refresh Interval [65528]
Trfc1 [384]
Trfc2 [384]
Trfcsb [384]
Trtp [12]
TrrdL [8]
TrrdS [4]
Tfaw [32]
TwtrL [12]
TwtrS [6]
TrdrdScl [5]
TrdrdSc [1]
TrdrdSd [6]
Trdrddd [6]
TwrwrScl [6]
TwrwrSc [1]
TwrwrSd [8]
TwrwrDd [1]
Twrrd [7]
Trdwr [18]
IBUF_LPWR_MODE [Enabled]
ADDR_CMD_MODE [UnBuf]
M_ORDERING [STRICT]
S_COL_WIDTH [Auto]
MC_SVA_TRIM0 [Auto]
MC_SVA_TRIM1 [Auto]
MC_SVA_TRIM2 [Auto]
MMCM_MULT_F [Enabled]
CA ODT GroupA [Auto]
CK ODT GroupA [Auto]
CS ODT GroupA [Auto]
CA ODT GroupB [Auto]
CK ODT GroupB [Auto]
CS ODT GroupB [Auto]
Processor ODT P state mode [Sync all P-states]
Processor ODT Impedance Pull Up P0 [Auto]
Processor ODT Impedance Pull Down P0 [Auto]
Processor DQ drive strengths Pull Up P0 [Auto]
Processor DQ drive strengths Pull Down P0 [Auto]
Dram ODT Impedance RTT_NOM_WR P0 [Auto]
Dram ODT impedance RTT_NOM_RD P0 [Auto]
Dram ODT impedance RTT_WR P0 [Auto]
Dram ODT impedance RTT_PARK P0 [Auto]
Dram ODT impedance DQS_RTT_PARK P0 [Auto]
Dram DQ drive strengths Pull Up P0 [Auto]
Dram DQ drive strengths Pull Down P0 [Auto]
Proc CS Drive Strength [30 ohm]
Proc CK Drive Strength [30 ohm]
Proc CA Drive Strength [30 ohm]
Proc Data Drive Strength [48 ohm]->[48 ohm][48 ohm][48 ohm]----->[34.3 ohm][40 ohm] [48 ohm]
CPU On-Die Termination [32 ohm]--->[32 ohm][30 ohm][34.3 ohm]->[36.9 ohm][53.3 ohm][43.6 ohm]
DRAM Data Drive Strength [40 ohm]->[34 ohm][34 ohm][34 ohm]--->[48 ohm] [48 ohm] [40 ohm]
Rtt Nom Wr [RZQ/6 (40)]-----------> [40] [40] [40] [40] [40] [40]
Rtt Nom Rd [RZQ/6 (40)]-----------> [40] [40] [40] [40] [40] [40]
Rtt Wr [RZQ/5 (48)]-------------------> [40] [48] [48] [48] [48] [48]
Rtt Park [RZQ/5 (48)]----------------> [48] [48] [48] [48] [48] [48]
Rtt Park Dqs [RZQ/6 (40)]---------> [40] [40] [40] [40] [40] [40]
Power Down Enable [Enabled]
Memory Context Restore [Disabled]
UCLK DIV1 MODE [UCLK=MEMCLK]
CA Tx Phase Shift Clk [Auto]
CS Tx Phase Shift Clk [Auto]
CK Tx Phase Shift Clk [Auto]
CA Rx Phase Shift Clk [Auto]
CS Rx Phase Shift Clk [Auto]
CK Rx Phase Shift Clk [Auto]
FIFO Wr En Fine Delay [1]
POC Sample PD [Disabled]
Bank Swap Mode [Auto]
Mem Over Clock Fail Count [Auto]
Prochot VRM Throttling [Enable]
Peak Current Control [Enable]
Medium Load Boostit [Enabled]
Precision Boost Overdrive [Manual]
PPT Limit [180]
TDC Limit [125]
EDC Limit [170]
Precision Boost Overdrive Scalar [Manual]
Customized Precision Boost Overdrive Scalar [8x]
CPU Boost Clock Override [Enabled (Positive)]
Max CPU Boost Clock Override(+) [100]
Per-Core Boost Clock Limit [Enabled]

Voltage training [Enabled]
CPU Load-line Calibration [Auto]
CPU Current Capability [Auto]
CPU Power Duty Control [Extreme]
CPU Power Phase Control [Manual]
Power Phase Response [Ultra Fast]
VDDSOC Current Capability [Auto]
VDDSOC Power Duty Control [Extreme]
VDDSOC Power Phase Control [Manual]
Power Phase Response [Ultra Fast]
Performance Bias [None]
Clock Spread Spectrum [Disabled]
Stretch mode for L3 DFLL [Enabled]
1.8V PLL Voltage [Auto]
1.8V Standby Voltage [Auto]
Misc_ALW [Auto]
Chipset 1.05V [Auto]
Algorithm 1 [Disabled]
Algorithm 2 [Disabled]
Algorithm 3 [Disabled]
CCD Priority Memory Activity Threshold [1070]
CCD Priority Hysteresis [Auto]
Cooler Efficiency Customize [Keep Training]
Cooler Re-evaluation Algorithm [Very inclined to update]
Optimism Scale [100]
CPU Core Voltage [Auto]
CPU SOC Voltage [Auto]
CPU VDDIO / MC Voltage [1.40000]
Misc Voltage [Offset Mode]
- Offset Mode Sign [+]
- Misc Voltage Offset [0.05200]
VDDP Voltage [1.066]
High DRAM Voltage Mode [Disabled]
DRAM VDD Voltage [1.40000]
DRAM VDDQ Voltage [1.40000]
VDDG CCD Voltage [Auto]
VDDG IOD Voltage [Auto]
PMIC Force Continuous Current Mode [Enabled]
PMIC Voltages [By per PMIC]
PMIC1 SPD HUB VLDO (1.8V) [Auto]
PMIC1 SPD HUB VDDIO (1.0V) [Auto]
PMIC1 Memory VDD Voltage [1.40000]
PMIC1 Memory VDDQ Voltage [1.40000]
PMIC1 Memory VPP Voltage [Auto]
PMIC1 Memory Voltage Switching Frequency [Auto]
PMIC1 Memory Current Capability [Auto]
PMIC3 SPD HUB VLDO (1.8V) [Auto]
PMIC3 SPD HUB VDDIO (1.0V) [Auto]
PMIC3 Memory VDD Voltage [1.40000]
PMIC3 Memory VDDQ Voltage [1.40000]
PMIC3 Memory VPP Voltage [Auto]
PMIC3 Memory Voltage Switching Frequency [Auto]
PMIC3 Memory Current Capability [Auto]
Security Device Support [Enabled]
SHA256 PCR Bank [Enabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
Physical Presence Spec Version [1.3]
Firmware TPM switch [Enable Firmware TPM]
Erase fTPM NV for factory reset [Enabled]
Password protection of Runtime Variables [Enable]
PSS Support [Enabled]
NX Mode [Enabled]
SVM Mode [Enabled]
Above 4G Decoding [Enabled]
Resize BAR Support [Enabled]
SR-IOV Support [Enabled]

DRAM PDA Enumerate ID Programming Mode [Sequential PDA enumeration mode]
TX DFE Taps [4 Taps]
PPT Control [Auto]
DDR Training Runtime Reduction [Auto]
Rx Burst Length [8x]
Tx Burst Length [8x]
RX2D_TrainOpt [Auto]
TX2D_TrainOpt [Auto]
RX DFE Taps [4 Taps]
MBIST Enable [Enabled]
MBIST Test Mode [Both]
MBIST Aggressors [Enabled]
MBIST Per Bit Slave Die Reporting [Enabled]
Pattern Select [Both]
Pattern Length Select [Auto]
Aggressor Channel [7 Aggressor Channels]
Memory Context Restore [Disabled]
Read Drift Adjustment [Auto]
Read Drift Adjustment P0 [Auto]
Read Drift Adjustment P1 [Auto]
Read Drift Adjustment P2 [Auto]
Read Drift Adjustment P3 [Auto]
Write Drift Adjustment [Auto]
Write Drift Adjustment P0 [Auto]
Write Drift Adjustment P1 [Auto]
Write Drift Adjustment P2 [Auto]
Write Drift Adjustment P3 [Auto]
Pre-boot DMA Protection [Auto]

TDP Control [Manual]
ECO Mode [Disable]
TDP [140000]
PPT Control [Manual]
PPT [180000]
Thermal Control [Manual]
TjMax [74]
TDC Control [Manual]
TDC_VDDCR_VDD [125000]
EDC Control [Manual]
EDC_VDDCR_VDD [170000]
Fan Control [Auto]
VDDP Voltage Control [Auto]
Infinity Fabric Frequency and Dividers [2167 MHz]

Active Memory Timing Settings [Auto]
Processor CS drive strengths [Auto]
Processor CK drive strengths [Auto]
Processor CA drive strengths [Auto]
Processor DQ drive strengths [Auto]
Processor ODT impedance [Auto]
Dram DQ drive strengths [Auto]
Dram ODT impedance RTT_NOM_WR [Auto]
Dram ODT impedance RTT_NOM_RD [Auto]
Dram ODT impedance RTT_WR [Auto]
Dram ODT impedance RTT_PARK [Auto]
Dram ODT impedance DQS_RTT_PARK [Auto]
Power Down Enable [Disabled]
RX2D_TrainOpt [Auto]
TX2D_TrainOpt [Auto]
RX DFE Taps [4 Tap]
TX DFE Taps [4 Tap]
DDR5 Nitro Mode [Enable]
DDR5 Robust Training Mode [Enable]
Nitro RX Data [2]
Nitro TX Data [3]
Nitro Control Line [1]
Nitro Rx Burst Length [8X]
Nitro Tx Burst Length [8X]
Nitro DFE Vref Offset Limits [Auto]
Infinity Fabric Frequency and Dividers [Auto]
UCLK DIV1 MODE [UCLK=MEMCLK]
Precision Boost Overdrive [Auto]
VDDG Voltage Control [Auto]
VDDP Voltage Control [Auto]
SoC/Uncore OC Mode [Enabled]

What is voltage training in LLC? What is training? New option without description

@SAFEDISK Can you answer this question?

dinosaur
Level 9

I just updated from UEFI 2201 to 2307 on my X670E Hero, and found a bug in that latter BIOS which caused crashes shortly after each reboot: the "Power Down Enable" setting that is normally automatically set from ASUS' advanced memory settings when you enable "Memory Context Restore" was indeed set in 2307 but was contradicted by the (duplicate/mirror) "Power Down Enable" setting in the AMD overclocking menu, and the latter took precedence, even after several resets and power off/power on cycles. When I found out (those crashes were typical of PD/MCR issues I encountered in the past and the two settings in ASUS and AMD respective menus were contradicting themselves), changing that setting in AMD's menu to "Enabled" did fix the problem and prevented any further crash...

On a side note, I still cannot comprehend why the Hell the MCR feature requires PD to be enabled: the latter should not influence the least the memory timings, and when MCR is disabled, each training (which then happens at each boot and is particularly painful since so long to complete) always results in the exact same memory timings anyway. AMD and ASUS should really fix this bug once and for all, so that we can set MCR to enabled and PD to disabled !!!

EDIT: 2308 is also affected by this bug...

AMD claimed to have fixed it in AGESA 1.0.8.0. Not sure what they were smoking because it still hasn't been fixed.

I've never been able to check this because my memories don't do well with "Power Down" to [disable].

magix86
Level 10

Hello,

lot of bios from Asus give me this error when i check the archive or uncompress them with 7Zip.

No error with windows Extract nor Winrar, no error in the last beta bios when extract with winzip.

Could this error corrupt the bios file and give us so lot of ramdom unexplicable bug ?  What are you thinking of it ?

(Really sorry for my pure Franglish, i try, but it's far in my student memory, thanks google translate to help me a little).

magix86_0-1725606004443.png

The last beta check is ok:

magix86_1-1725606085539.png

 

Bye

Magix86