One can certainly go insane trying to figure out how bandwidth is shared among PCIE slots, M.2 sockets, and SATA ports, but it is usually in the manual even if cryptically described. I have found that it helps to know which PCIE, M.2 and SATA ports are controlled by the CPU versus which are controlled by the chipset as bandwidth conflicts appear to be confined within CPU versus chipset connected ports. To help you with this, CPU-controlled PCIE slots are usually one color while chipset-controlled PCIE slots are a different color (usually black). And I think that "shared bandwidth" usually means that if you occupy a PCIE slot, then any shared M.2 socket or SATA port becomes disabled. It is insane, but figuring it out is part of the fun of building it yourself. It feels so good when the pain stops:)
