DON'T MIX RAM KITS, but if you do/did... ;-)

[cekim]

See title and the sticky, it seems people are having trouble getting this message.

https://rog.asus.com/forum/showthread.php?57038-Don%92t-combine-memory-kits!-The-meat-and-potatoes-o...

However, I thought I'd share and ask if there were others who did and what you had to do for the sake of causing trouble, I mean helping other people make the most of 2 mis-matched kits. What did you need to do?

I busted out of 32G and bumped one machine up to 128G. As such, I now had a shiny new 32G cas 14 3000 kit with no home. I could sell it, or I could experiment. This is an X99Pro system, but for my purposes, my RVE and x99PRO's behave very similarly, so just squint and imagine the white and grey are red.

The X99 ASUS memory layout on these two boards (with the I/O panel on your left) is:
A1 A2 | B1 B2 | CPU | C1 C2 | D1 D2

You'll notice in the BIOS that A/B and C/D are parameterized independently in various places. I honestly don't know if this fully reflects how the hardware is partitioned (one of the reasons for this thread is to ask), however, I am assuming the BIOS writers did this for a reason (which is that they had 2 sets of registers to write).

1. I began with the assumption that the best chance of success was to keep the kits isolated AB = kit 1 CD = kit 2
2. Since SPD is going to get iffy to bad (see sticky), I manually entered the slower of the two kit's values.
3. I've had no success getting 3000 to stable with any kit I have had on multiple processors/board (maybe I suck at DDR OC?), but all work well at 2800, so I went with that...

I used the "memOK" button after a full-power cycle and it still took a few reboots to convince the BIOS to re-train.

and voila! 64G 2800 cas 14 1.35v 100BCLK:

[Avenger411]

Hey,

Just so you don't get everybody's hopes up. A/B channels have nothing to do with you succeeding (from what i've read). It is possible for this to work, you have been lucky. Good job.

Max

[cekim]

Avenger411 wrote:
Hey,

Just so you don't get everybody's hopes up. A/B channels have nothing to do with you succeeding (from what i've read). It is possible for this to work, you have been lucky. Good job.

Max

Well, that's what I am after in posting this. A given DDR PHY only cares about what is connected directly to it and its configuration parameters. Any one of the three in the chain here (Intel, AMI and Asus) could have broken the ability for the channels to function independently by:

a. provisioning only 1 or 2 registers (AB CD or even ABCD) for a given parameter.
b. exposing only 1 or 2 registers or memory locations written to registers by other code such that the BIOS lacks "knobs" to turn for the channels.

Maybe someone here knows exactly where that breaks, but I'm not trying to get anyone's hopes up. Just learn about this system and have fun. If you got past the title, the sticky and my warning, well then, I can't help you. 😉

[Arne_Saknussemm]

DON'T MIX RAM KITS, but if you do/did... 😉

See title and the sticky, it seems people are having trouble getting this message.

https://rog.asus.com/forum/showthrea...atoes-overview

Hmmm while the ranks are split AB / CD the recommended slots are A1 B1 / D1/ C1 on the RVE.....I kind of assumed if you mixed kits to keep one kit on the 1 slots and one on the 2 slots.....not one left of CPU one right....

Now I wonder how things are set up....maybe power supply is left and right but one quad channel is across No.1 slots and one across No.2

I need breakfast and a cup of tea :confused:

[cekim]

A1 B1 C1 D1 gets something addressable on each channel's pins, so it maximizes the chance that you can spread the memory load over the 4 channels rather than bottlenecking behind one controller now shared amongst the cores for any given read/write.

It doesn't imply anything about commonality of timing. In fact, if I understand the structure of this chip correctly, that is 4 distinct controllers and their PHYs, so if they share any parameters it was because intel, AMI or Asus "wired" them up (physically or in software) to the same control register(s), but at some level on the die, they are separate gates.

[cekim]

Update: so far so good in linux:

01:45:51 up 1 day, 1:58, 3 users, load average: 15.83, 8.93, 3.72
KiB Mem : 65875304 total, 348336 free, 63117712 used, 2409256 buff/cache
KiB Swap: 16449532 total, 16371784 free, 77748 used. 2433856 avail Mem

stressapp run for giggles:
2016/04/05-01:51:49(EDT) Stats: Found 0 hardware incidents
2016/04/05-01:51:49(EDT) Stats: Completed: 20525916.00M in 600.05s 34206.84MB/s, with 0 hardware incidents, 0 errors
2016/04/05-01:51:49(EDT) Stats: Memory Copy: 20525916.00M at 34209.01MB/s
...
2016/04/05-01:51:49(EDT) Status: PASS - please verify no corrected errors


Also, in the BIOS DRAM timings, I saw the post-training result had different values for A/B than it did for C/D and those values corresponded to roughly what I would have expected for the 2 kits (one is 3000 CAS 15 the other is 3000 CAS 14 - running both at 2800 cas 14).

Since I haven't needed/tried to use different voltages for the two kits (they are both 1.35), I might try mixing things up and see what happens.

I will say, and I've seen this before in my various setups, I set both the boot and eventual DRAM voltages because if I don't I randomly see horrible things (like 1.5V !!!). Nope, sorry, no auto for you!