CDK, CUDIMM & Memory Gears - What You Need to Know

[Silent_Scone]

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Signal Integrity is the name of the game

The further we push any frequency, the more important the signal margin becomes. This is especially true for DRAM as higher frequencies intensify the demand for precise signal timing, and without sufficient margin, errors occur. At its core, this is the system 'flipping a bit'—an unintended change in a data bit from 0 to 1 or vice versa.

Making DIMMs less dim - What is a CUDIMM?

JEDEC’s new JESD323 standard introduces CUDIMMs—a variation of unbuffered DIMMs with an added Clock Driver (CKD) on the module. This CKD regenerates a clean clock signal directly on the DIMM. Normal UDIMMs rely on the CPU IMC for this purpose, which isn't ideal when the signal is being driven elsewhere.

For those who aren't aware, moving this signal to the DIMM isn't anything new. RDIMM (Registered DIMM) have been around in the workstation space for decades and also employ a CKD. You can consider CUDIMMs to be a more simplified version of this, as unlike CUDIMMs, RDIMMs also drive the command and address buses rather than simply the clock signal. RDIMMs also all feature ECC (Error-Correcting Code) which helps detect and correct single-bit memory errors to prevent data corruption.

The simplified approach of CUDIMMs helps keep costs down in the consumer space, and also has a positive impact for enthusiasts, as cleaner signal integrity allows for more signal margins. For that reason, speeds as high as 10,000MT/s are now not altogether abnormal and do not require any form of exotic cooling.

CUDIMMs are targeted for DDR5-6400 - DDR5-7200 depending on the vendor.

Can I use CUDIMMs on older DDR5 platforms?

CUDIMMs are designed to be drop-in compatible with current DDR5 systems, using the same 288-pin connector. Platforms that don't support these features will simply bypass the CKD. This is done (as the name suggests) by bypassing the CKD signal (PLL Bypass).

CUDIMM and CKD Clock Signal Handling

• CKD (Clock Driver) stabilizes the clock signal, which is the base for data read/write operations.
• CKD increases the frequency margin, depending on the memory vendor.
• Currently, all CUDIMM modules operate by default in Single PLL mode.
• For systems using CUDIMM, configure CKD under Skew Control in UEFI, with available modes:
  • Single PLL Mode: Default for most CUDIMMs, used during initial POST.
  • Bypass Mode: Bypasses the CKD (same as conventional UDIMM mode).
  • If POST fails in Single PLL Mode, the system will automatically attempt to switch to Bypass Mode [to check if CKD is causing instability]
    

Is there a latency penalty depending on the mode?

Single PLL or Bypass mode does not incur a latency penalty. Results are within run-to-run variance. 

Example:

V-Color Manta DDR5 8800MT CU-DIMM (XMP)

Single PLL

Bypass Mode

Gear Ratios (Gear 2 & Gear 4)

• Gear Ratio: Represents Memory Controller to DRAM frequency ratio.
• Accessible under Extreme Tweaker > Memory Controller : DRAM Frequency Ratio.
• Until DRAM frequency of 9066, Gear 2 (1:2) is the default mode.
• Memory Gearing applies to both UDIMM and CUDIMM.

Setting Memory Controller Ratio to DRAM Ratio:

• The board will automatically assign the correct ratio depending on the applied frequency.
• Manual adjustment can be found under Extreme Tweaker > Memory Controller: DRAM Frequency Ratio

CPU-Z Example: Gear 2 9000MT/s

CPU-Z Example: Gear 4 9000MT/s

Is there a latency penalty for running in Gear 4 over Gear 2?

Yes, a higher divider reduces the memory controller frequency. As a result, there is more delay in synchronising data between the CPU and memory. Best performance is found between 8000MT/s and 8800MT/s in Gear 2, whilst some reasonable CPUs used in conjunction with the  ROG Z890 Apex can run higher. For 9000MT/s G2 and above, a reasonable memory controller is needed.

Gear 2

Gear 4

Stability Examples

V-Color Manta DDR5 8800MT CU-DIMM (XMP)
Z890 Apex - 285K 
Gear 2 8800MT/s XMP I Profile
(Sub-timings board controlled)

V-Color Manta DDR5 8800MT CU-DIMM
Z890 Apex - 285K 
Gear 2 8933MT/s
(Sub-timings board controlled)

V-Color Manta DDR5 8800MT CU-DIMM
Z890 Apex - 285K 
Gear 2 9000MT/s
(Sub-timings board controlled)

V-Color Manta DDR5 8800MT CU-DIMM
Z890 Apex - 285K 
Gear 2 9000MT/s 
(Tuned Sub-timings)