1 ACCEPTED SOLUTION
Accepted Solutions
Hi @Int8bldr 😎 Here is 4001 modded BIOS specific only Skylake X CPUID 50654 with 02007108 microcode mate. I used testing it with Windows Insider Canary build without problem. Only on AVX2/AVX512 penalty performance hit that can't be solve by 02007108 microcode is only weak point.
Download Link :: https://drive.google.com/file/d/1sJPw3lzeLRGeWbyOl-On6OlXxqqEB7Pm/view?usp=sharing
Caution :: The Modded BIOS support only Skylake SP/X/W CPUID 50654 for internally test with Windows Insider Preview Canary Edion under developer agreement with Intel and Microsoft by developer only. So there are no support in case of failed boot or system damage at all. Trying by your own risk. Intel and Microsoft didn't responding for any error instability malfunction all case for any users experience.
The Downfall Vunerable still nightmare for newier architect from Intel too. Thus Lion Cove and Skymont microarchitect had been release without Hyperthreading were from these root cause indeed. Due Hyperthreading function always call " GATHER Instruction " to perform FMA3 /AVX2/AES/AVX512/VNNI instruction processing on Intel complex FPU design. Even Redwood Cove on Core Ultra 100 Series and Granite Rapid AP/W/XSP will be lost there peak FPU performance due " Downfall " vulnerable patch according to lastest Intel document below.
All affected Intel CPU list on " Downfall " Vulnerable lastest update 2024/09/30
By contrast AMD FPU platform split FADD and FMUL each pipeline were luckily automatic " Downfall " mitigation by its design. Look like AMD were behind " Downfall " attackers to shooting out Intel most strength point on it CPU design aka " Intel FPU's FMA3 Unit "
In the past Intel winning over AMD on Intel FMA3 that use 3-clock latency to perform FMA instruction AMD loss with there FMA4 that use more than Intel 1 clock latency. Today AMD strike back with " Downfall " vulnerables that cause Intel FPU performance penalty hit by 30-50%. So It hard to believe that AMD wasn't stand behind or be a partner of " Downfall " attacks.
On Lion Cove and Skymont Design , Intel had learning more their loss on " Downfall " The FPU of both Lion Cove Core and Skymont core had been change and disable Hyperthraeding to avoid " GATHER " Instruction call.
Lion Cove FPU had been redesign to prevent all folks above from AMD and " Downfall " teams attack again. Intel was split there FPU into ZEN styles. If it has been attacking by " Downfall " team AMD CPU will be impact too. It was the answer from Intel Oregon team shortly.
So no more " GATHER " instruction need and no more " Downfall " on Lion Cove at these point. Thus
" No performance Penalty hit anymore No microcode work around No more complaint "
Skymont also complied same target reduce using " GATHER " Instruction by split it FPU design like Lion Cove too.
That's all folks today. Thank you ASUS ROG Forum teams and every X299 friends who still running today.
Hi @Int8bldr 😍
1. Yes! I'm happy with Intel engineer Skylake X team best trying. They can't bring back AVX2/AVX512 Performance hit on " Downfall " mitigation however they had reduce Core to Core latency on mesh interconnect node as best as they can do. So when we utilized the 020007108 microcode with 4001 BIOS. You'll see the core scalable ratio were increse from 02007006.
Setup method " Load Optimized Default " , XMP Overclock Profile DDR4 3200 16-18-18-36 , ASUS Multicore Enhancement AUTO "
2. The modded BIOS contain recently module as update as can be for Skylake X (CPUID 50654 Specifically )
3. Look like Intel engineer trying there best on Core-to-Core latency deductive. 020007108 microcode provide better multicore scalable enhancement. But those 020007006 and 020007108 didn't bring back Skylake X AVX2/AVX2 Performance yet. Skylake X loss around 31.42% on AVX512 and 48.88% on AVX2 Performance when testing with CPU-Z 19.0.1.64 (AVX2 Beta) and CPU-Z 19.0.1.64(AVX512 Beta) . Thus when testing with Geekbench 6 Cinebench R23/R24 ( used of heavily AVX2 instruction our Skylake X / Cascade Lake X look like the drunk boy inferior even old school ARM64 ) From best static I'd collect.
When you compare the three picture above ( W11 25H2 / W11 24H2 / W10 Last Dev build.) you'll notice that the multicore scalable on newier microcode always better on CPU-Z 17.01.64 that mixing X87/MMX/SSE4.2 instrucions measurement. The 02007108 can be archived 22.00+ scalable ratio which higher than old school microcode. In contrast , on AVX2/AVX512 performance 02007108 and 02007006 microcode perform worse when compare with older microcode.
Hi @Int8bldr 😎 Here is 4001 modded BIOS specific only Skylake X CPUID 50654 with 02007108 microcode mate. I used testing it with Windows Insider Canary build without problem. Only on AVX2/AVX512 penalty performance hit that can't be solve by 02007108 microcode is only weak point.
Download Link :: https://drive.google.com/file/d/1sJPw3lzeLRGeWbyOl-On6OlXxqqEB7Pm/view?usp=sharing
Caution :: The Modded BIOS support only Skylake SP/X/W CPUID 50654 for internally test with Windows Insider Preview Canary Edion under developer agreement with Intel and Microsoft by developer only. So there are no support in case of failed boot or system damage at all. Trying by your own risk. Intel and Microsoft didn't responding for any error instability malfunction all case for any users experience.
The Downfall Vunerable still nightmare for newier architect from Intel too. Thus Lion Cove and Skymont microarchitect had been release without Hyperthreading were from these root cause indeed. Due Hyperthreading function always call " GATHER Instruction " to perform FMA3 /AVX2/AES/AVX512/VNNI instruction processing on Intel complex FPU design. Even Redwood Cove on Core Ultra 100 Series and Granite Rapid AP/W/XSP will be lost there peak FPU performance due " Downfall " vulnerable patch according to lastest Intel document below.
All affected Intel CPU list on " Downfall " Vulnerable lastest update 2024/09/30
By contrast AMD FPU platform split FADD and FMUL each pipeline were luckily automatic " Downfall " mitigation by its design. Look like AMD were behind " Downfall " attackers to shooting out Intel most strength point on it CPU design aka " Intel FPU's FMA3 Unit "
In the past Intel winning over AMD on Intel FMA3 that use 3-clock latency to perform FMA instruction AMD loss with there FMA4 that use more than Intel 1 clock latency. Today AMD strike back with " Downfall " vulnerables that cause Intel FPU performance penalty hit by 30-50%. So It hard to believe that AMD wasn't stand behind or be a partner of " Downfall " attacks.
On Lion Cove and Skymont Design , Intel had learning more their loss on " Downfall " The FPU of both Lion Cove Core and Skymont core had been change and disable Hyperthraeding to avoid " GATHER " Instruction call.
Lion Cove FPU had been redesign to prevent all folks above from AMD and " Downfall " teams attack again. Intel was split there FPU into ZEN styles. If it has been attacking by " Downfall " team AMD CPU will be impact too. It was the answer from Intel Oregon team shortly.
So no more " GATHER " instruction need and no more " Downfall " on Lion Cove at these point. Thus
" No performance Penalty hit anymore No microcode work around No more complaint "
Skymont also complied same target reduce using " GATHER " Instruction by split it FPU design like Lion Cove too.
That's all folks today. Thank you ASUS ROG Forum teams and every X299 friends who still running today.
