New Microcode of Skylake X 50654 fixing AVX2/AVX512 performance penalty is coming soon.

[restsugavan]

According to Intel 02007006 microcode DATE 2023-03-06 for Skylake X SKUs ( CPUID 50654 ) patched on R6E 3801 Official BIOS. The microcode above prevented " DOWNFALL " vulnerable issue attack on " GATHER " instruction of Skylake X Series CPU. ( aka Core i9 78XX-7980XE ).

Even it prevented " DOWNFALL " vulnerable issue efficiently but on other hand it cause side effect of Skylake X CPU performance. Specially FPU units those microcode slow down FMA3/AVX2/AVX512 performance penalty 30-50%. 

Now Intel's engineer had been complete working on these issue.

The new microcode was publish on 2023-07-28. To bring back Skylake X FPU performace. 😁 

[Int8bldr]

Granit Rapids is the first of a new generation of CPUs that will provide large improvements across the board of old x86, i64 and new AVX10.1 ISA standards. One thing which is interesting for the old x86, i64 instruction set is that Intel is doubling the amount of integer registers from 16 to 32 available for all. This only happens like every decade or so since you are messing with the core of the ISA. Allowing compilers to use more registers will offload memory transfers at the most basic level for every method and function call in every program that gets recompiled - since less need to be stored on the stack. Intel has published quite a bit about these changes (on their web site) and if they can pull off all of that and have Granit Rapids products in the HEDT space out this year, it will be a great year to upgrade.

But we will see. Xeon for the Data Center comes first, then Xeons for Workstations and very last comes the potential HEDT SKUs - or NOT, as we have seen with ice lake, sapphire rapids, emerald rapids which had no corresponding HEDT derivative - until now...

[restsugavan]

LGA 4677 was going to be EOL. I hope Intel playing LGA 4710 like LGA 2066 Era.

We will get Diamond Rapid featuring 128 Lion Cove Cores which first 64KB I-Cache 64KB D-Cache 3M L2 Cache 8M L3 Cache. It the first AVX1024 instructions support CPU from Intel.

[Int8bldr]

Let us all hope that there will be a new line of rampage VII extreme with LGA4710 starting with Granit Rapids and then a few more generations, i.e. Dimond Rapids etc that are motherboard socket LGA4710 compatible. Just like the 79xx, 99xx, 109xx were MB and 2066 compatible. 128 P cores would be fantastic! don't care for the E core one bit. 

[Int8bldr]

and I would be first in line if there is a Rampage VII Extreme / Granit Rapids CPU offering this year. if at a decent price of course 😁.

[PanosXidis24]

okay so

10900X 4.8GHZ UNCORE 3.2GHZ CIBENECH R15 MCODE LATEST 3605 2587CB

10900X 4.8GHZ UNCORE 3.2GHZ CINEBENCH R15 MCODE OLDEST 0010 2739CB

so always newer microcode hit perfomance guys!!!

[tistou77]

It seems that this microcode lengthens the boot time (Task Manager => Startup)
If anyone who put this ucode, can check

Thanks

[tistou77]

For info, after several tests, it wouldn't come from ucode
I don't see what this could be (same options in bios)...