Maximum of Mesh Interconnect Performance by Emerald Rapid Micro architect Max out LGA 4677

[restsugavan]

Intel Mesh Interconnect Gen 1 from Skylake X ERA 2017

 Legendary Intel Mesh Interconnect used on our Skylake X through Sapphire Rapid almost L3 cache bound. In most intensive computation via Intel AVX512 instructions. The bound cause insufficient cache size to do 2 and above complex instructions on once time. Limited L3 cache size maybe bring pipeline stalling on port 0+1 and sometime also bring other output on port 5 slowing down following at last.

Intel continuing increse L3 cache from generation by generation

After debate on many CPU engineering forum. Finally Intel had been grant to increse L3 cache size over Emerald Rapid to fixing L3 cache bound issue. These may eliminate AVX512 issues above nearly 100%. 

Finally The L3 cache size being bigger than L2 cache fixing all L3 cache bound issue.

Intel going to show its " Emerald Rapid CPU " on Intel Innovation 2023 Forum next month. Let's see the best of mesh interconnect over ringbus after 7 years release to public since Skylake X microarchitect.

[restsugavan]

New Redwood Cove Microarchitect Intel First 64K L1 I-Cache 64 K D-Cache 16-way set associative.

Empire Strike Back !!! via LGA 7529 Tons of killing features.

New Intel Granite Rapid LGA 7529 Features 128 Redwood Cove P-Core with 2MB L2 Cache 4MB L3 Cache Modular Mesh Fabric

12 Channel DDR5 Upto 8800MT/s 136 Lane PCIe 5.0 CXL 2.0

Next generatopm Mesh Fabric clocking up 4GHz + against 2.4GHz 1st gen.

 Next generation Mesh Fabric Speed up to 4+ GHz and beyond compare to 2.4/3.2 GHz on 1st gen on our Skylake X

136 Lane PCIe 5.0 CXL 2.0 SoC Enhance Design

 Increase I/O from 80 lanes PCIe 5.0 on LGA 4677 to 136 lanes PCIe 5.0 on LGA 7529 platform

New Siera Glen Microarchitect

New 144 Siera Glen E Core with 4MB L2 Cache 3MB L3 Cache Modular Mesh Fabric

12 Channel DDR5 upto 8800MT/s 136 Lane PCIe 5.0 CXL 2.0

Building on Intel 3 Node (Intel 7nm EUV+)