Intel release AVX10A Enable AVX512 support both P-Core and E-Core. Skylake X Performance uplift.

[restsugavan]

Intel SIMD ISA Family and Features.

Our Skylake X / Cascade Lake X / Cooper Lake X will shift to " Intel AVX10.1 "

According from anandtech

" 

Intel is committing to supporting a maximum vector size of at least 256-bit on all Intel processors in the future. Still, it remains to be seen which SKUs (if any) and the underlying architecture will support full 512-bit vector sizes in the future, as this is something Intel hasn't officially confirmed at any point.

The meat and veg of Intel's new AVX10 instruction set will come into play when AVX10.2 is phased in, officially bringing 256-bit instruction vector support across all cores, whether performance and/or efficiency cores. This also marks the inclusion of 128-bit, 256-bit, and 512-bit integer divisions across both the performance and efficiency cores, and as such, will support full vector extensions based on the specification of each core. " 

New Intel AVX10.1 Library Enhance Skylake X micro-architect and above uplift.

Now Intel release new math kernel library enhance our Skylake X / Cascade Lake X / Cooper Lake X series based on Skylake X micro architect.  From this footprint Intel Skylake X with 2 x FMA  512-bit Unit going to be performance uplift soon.

Golden Skylake X will be back!

[PanosXidis24]

what is that exactly?

[Int8bldr]

Unfortunately, intel's new naming convention or standard or what ever, is super unclear.

The main problem I immediately see is that AVX512 code is not guaranteed to execute on any of the 10.1 or 10.2 standards since AVX512 support it is optional in 10.1 and 10.2. 

What should a programmer that code for AVX-512 do? Well the simply answer is that he has to switch to 256 standards since that is the only one that is guaranteed to work. 

effectively killing AVX512. Stupid since AVX512 is super powerful!

sad.

[PanosXidis24]

yeah but what exactly is that? Its come with update windows or cpu microcode or bios?

[restsugavan]

According to  https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions....

Intel continuing to support our Skylake X Cascade Lake X Cooper Lake X as well with new Intel AVX10.

[PanosXidis24]

okay maybe with bios update

[Int8bldr]

AVX10.1 or 10.2 10.x is not about bios updates. This is about the instruction set that all future Intel CPUs will support. 

think of it as a revission of x86, x64, AVX,... AVX 512, and now for new CPUs going forward AVX 10.1 and AVX 10.2.

What intel is saying is that alll future generations of intel CPUs will support AVX10.1 and the next after that will support AVX10.1 instructions sets. 

My grip is that AVX512 is at 512 bit length standard is not guaranteed to be supported in any of these standards. AVX512 512 bit is optionally supported and the way I read that (this super confusing intel ISA standard update) is that AVX512 will be guaranteed to be supproted on Xeons like today since Skylake (which also include our x299 based core i9 79x0, 99x0 and 109xx) and on all future Xeons. But it is also saying that AVX512 will be included in "some" P cores in future cpus. what the h@lll does "some" mean and how the h@ll can intel expect anyone to program something for "some" CPUs without specifying what "some" means.

My interpretation is that only means that you can only be sure Xeons will execute code compiled to with AVX512 flag and any future non-Xeon client is NOT guaranteed to execute the same AVX512 complied executable. And that sucks majorly!

[restsugavan]

Don't worry @Int8bldr . Intel is continue developing P-Core micro architect first priority.

From Xeon Scalable and Core X Series solution. P-Core are superset of E-Core series both feature and micro architect enhancement.

From now we've Golden Cove -> Redwood Cove -> Panther Cove ( First AVX 1024 , AMX2 ) -> Next Gen. both support 2 x FMA Units.

So. AVX512 is going on the folks. 

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