Intel may take on ZEN 5 with LGA 1700 long a wait legend " Bartlett S " CPU

[restsugavan]

According to lastest plan of Intel consumer desktop class last week. The company decide to take care ZEN 5 Skus with it premium killer chip " Bartlett S " CPU with contained only Raptor Cove P-Core with support both Intel Hyperthreading Technology and also AVX-512 with dual ports to battle with AMD Zen 5 camp. It will replace our Skylake X / Cascade Lake X LGA 2066 as well on HEDT secment in the same time.

Bartlett Lake S will be Plan B for Intel to handle AMD ZEN 5 and ZEN 5 X3D on Q1 2025. This is very interesting CPU for consumer those who want Intel Raptor Cove P-Core full performance and has full function of AVX512 and hyperthreading enable. It also support DDR4/DDR5 same as LGA 1700 CPU practice.  

Intel Raptor Cove Refresh P-Core will be take on ZEN 5 and ZEN 5c after final discussion of Intel teams 

Intel mystery ZEN 5 killer " Bartless S " SKU on plan

Bartlett S CPU will feature same P-Core as Raptor Lake Refresh on 14th Gen but due the TDP data above maybe we'll see 6+GHz Barlett S CPU for the production name Core i9 15900KS 6.4+ ETVB maybe it final best of 10nm+++ Super Fin lithography. 

[Int8bldr]

Interesting!
Thank you @restsugavan for sharing!

But, hmm... does Bartlett Lake-S only max out at 12 P-cores? not really a core i9-7980XE/10980XE 18 core replacement...

I would have expected a true v-next X platform to have at least peak at 32 P-cores if not 64 P-cores.

Seams reactive (panic mode?) to the generate more AI ops in a small consumer chip / not a HEDT X299 successor. Also, how many memory channels?

It's ironic that intel who designed the AVX512 vector language ISA and produced fantastic chips with 7980XE/9980XE/10980XE with dual FMAs per core, just dropped it in favor for including atom cores (aka E cores), now finds itself surpassed by ZEN5 which has much faster and better AVX512 FMAs just in time to generate the AI OPS we need in the AI boom. 

Intel had the advantage, decide to shift focus and now finds itself out dropping the ball, scrabbling to get back.

They should have trusted in their strategy and double down on and driven the AVX-512 hard to now be in a position to dominate the AI workloads... instead we get a 12 P-core in a LGA 1700 package in 2025 - really?

I will not be buying that... Very disappointing if true.

My next platform will likely be 48 or 64 P-cores only true HEDT/WS class AI OPS machine. If Intel cannot do that, I'll probably go AMD. it's been too many years but my 10980XE still holds up well. but for next get AI it will (is) start to show it's age soon.

[restsugavan]

Simple advice from Intel support guy advice to their datacenter customer.

According to LGA 1700 die physically it wide enough to put 16 Core Raptor Cove Refresh P-Core on CPU die like these picture below.

 Intel Raptor Cove Refresh Die fit on LGA 1700 packaging ( Intel 14900K Die for reference only ) .

 If we remove piece of junk Crestmont E-Core away it can contain 16 Core Raptor Cove P-Core Refresh easily as new " Bartlett Lake S " 

On Performance side Raptor Cove P-Core Refresh was base on Golden Cove Microarchitect with cutting down Intel AMX module. Add L2 cache from 1.25 MB to 2.0 MB and Add L3 cache from 2MB to 3MB on 256-bit Ringbus Interconnect running at 4500MHz speed.

16 Core Raptor Lake P-Core Refresh Bartlett Lake S had

16 x 32KB Instruction cache + 16 x 48KB L1 Data cache 16 x 2.0 MB L2 cache and 16 x 3.0 MB L3 cache.

It totally 1.280MB L1 cache 32MB L2 cache and 48MB L3 cache of 15900K . if this true it will overkill ZEN5 9950X  easily.

@Int8bldr  If we learn from AMD slide above ZEN5 memory sub system on it die always copied from our Skylake X / Cascade Lake X / Cooper Lake microarchitect 32 KB Instruction cache + 32 KB Data cache 1MB per core L2 cache 64MB Shared L3 cache. It totally 1.024MB L1 cache 16MB L2 + 64 MB L3 cache for ZEN 5 9950X.

Both AVX512 Fuctions of 9950X and Bartlett S Lake were comparable. If Intel playing price games as Cascade Lake X release practice.

AMD will get serious headache scenario indeed.

[Int8bldr]

still do no like this panic, reactive, quick and dirty Barlett-S even at 16 cores. 

If true, it's pathetic by intel to produce a max 16 core cpu where they cut away their main AI competitive advantage which is AMX, just to squeeze in 16 butchered cores on a too small piece of silicon area to match AMD.

Intel set the standard in 2017 with 7980XE, an 18-core state of the art CPU, and here we are 7 years later (will be 8 years in 2025) Intel launching a 16 core CPU as their top X SKU. Ridiculous!

As I wrote before, Intel should take their Granite Rapids Xeon and package it in a X format - exactly the same thing they did with 7980XE back in 2017! 

There is no way I will be buying a Barlett-S - I rather go AMD if this plays out.

[Int8bldr]

reading more about this here: https://videocardz.com/newz/intel-to-launch-bartlett-s-die-with-12-p-cores-for-lga1700-platform-in-j... , it's pretty clear to me that Barlett is Intel's attempt to compete with Ryzen 9 (9###X) with zen 5 cores - but ryzen 9 max out at 16 cores full zen5 P-cores. 

So Barlett-S is not competitive at only 12 P-cores and is certainly not the v-next HEDT X platform that I'm looking for.

What Intel should do is take one of their upcoming Xeon, (48, 64, 72, 96) core count Granit Rapids chips and package it in a v-next X#99 platform the same way they did it for 10980XE and 7980XE.

This Barlett-S is just a hard no. 

[restsugavan]

It was last minutes decided for Intel consumer desktop marketing division after their relationship to all vendors motherboard going worse scenario that wouldn't happen many years ago since Pentium 4 EE era. Many vendors decided to support AMD Camp Zen 5 SKUs rather than their Arrow Lake S. If we consider from Computex Taipei 2024 last month. Look like ASUS and ASRock both 2 brothers from Shih's family choose Lisa SU 's campaign instead Pat Gelsinger cleary.

Those from idiot statement that blame venders not complying their guidance to handle with Raptor Lake and Raptor Lake Refresh SKUs. Intel has not learn that how many years venders experience on their released platforms as partner any more. After finally they've find that the Intel thread director is the main cause of instability issue of Raptor Lake and Raptor Lake Refresh due it can't direct request of P-Core need data via Ringbus efficiently. Microcode patched release immediatly to all vendors but it will not help those vendor board director feel good anymore. The platform still has instability issue and some seriously scenario people find silicon-degrading after use that microcode like this video below.

[Int8bldr]

Seeing that intel in 2024 still updates the Skylake/Cascadelake X cpus uCodes (as a side effect of Xeon 2 scalable support) brings home another important point about how much more committed Intel is to their Xeon platform than their consumer platform in terms of long-term support. This is another great reason to use Xeons silicon to make the next gen HEDT X cpus. As we can see with 7980XE/10980XE (that were made from Xeon silicon), we still get serious uCode support today 5-7 years later. If we go down the path of Barlett-S butchered ARL/RPL silicon the long-term support will be as long as it takes intel to come out with the next gen after that - forcing consumer to upgrade. Another great reason to reject the Barlett-S approach. 

The 7980XE/10980XE approach was great providing state of the art high performance cores at high core count with Xeon level support at a HEDT/enthusiast price point! 

The Barlett-S butchered Granit rapids->ARL/RPL cores (hardly state of the art) in 2024 with medium/low core-count at best, with no Xeon counterpart -> a consumer level commitment and short-term support = FAIL!

[restsugavan]

@Int8bldr  Totally agree. However if we focus the real trouble of the upper video. Maybe it was limited of SuperFin Transistor that Intel used.

 Compare to 14nm lithography scaling on it refresh node such as 14+ nm(Skylake X) 14++nm ( Skylake X Refresh ) 14+++nm ( Cascade Lake X )