Right , L3 cache of Ringbus Interconnect can be scaling as well as Uncore speed due It topology styles.
Oppositing to Mesh Interconnect 1.0 itself they're 2 way bus (CHA) per core on uncore, thus the speed must be down from Ringbus to avoid traffic jam.
We can be maxing speed around 3.2-3.3 GHz for Skylake X SKU by increse cache and uncore voltage tweak. But it become unstable on some SKUs due
that voltage was not standard and Intel recommended.
Another disadvantage of Skylake X Microarchitect was Non-Inclusive cache machanism. On Skylake S and other architect that used Ringbus Interconnect.
Data on L1 were store on L2 and L3 cache too. Games and manytasks like this. But for Skylake X only L1 and L2 that data were store , L3 cache acting like
victim cache and uncore buffer too reduce latency of cache size. Games and manytasks require reload data a lot during we running it. L3 cache couldn't
helping L1 and L2 like Skylake S anymore due it was victim cache.
Just like Skylake X heavily use only L1 and L2 cache during re-load. Thank to it 512-bit wide databus here we'll not suffer a lot when oftenly re-load data.
However both L1+L2 data cache size was 32K+1024K when combined compare to Skylake S core that L1+L2+L3 cache size was 32K+256K+2048K. Thus
overall performance of Skylake X may inferior to Skylake S and other Ringbus Interconnect when using cache intensive task.
W11 25H2 27858.1000 Core i9 7980XE 02007206 MCE ME 11.12.97.2614 R6E Modified BIOS 4201 SAMSUNG OG9 FW 1020.0 SSD 970 EVO PLUS 1 TB x 3 NVIDIA RTX 4090 GAME READY 576.52 64GB GSKILL DDR4 3200MHz JBL 9.1 Sound Bar DTS-X
