11-16-2019
02:47 PM
- last edited on
03-06-2024
07:17 PM
by
ROGBot
11-20-2019 04:27 PM
| Field | SAFE t-values | BIOS Location: All under Extreme Tweaker > DRAM Timing Control |
| tCL | 14 | "DRAM CAS# Latency" |
| tRCDWR | 14 | Switch order |
| tRCDRD | 14 | Switch order |
| tRP | 14 | "DRAM RAS# PRE Time" |
| tRAS | 30 | "DRAM RAS# ACT Time" |
| tRC | 44 | |
| tRRDS | 4 | |
| tRRDL | 6 | |
| tFAW | 34 | |
| tWTRS | 4 | |
| tWTRL | 12 | |
| tWR | 12 | |
| tRDRD SCL | 4 | |
| tWRWR SCL | 4 | |
| tRFC | 307 | |
| tRFC (alt) | 312 | |
| tCWL | 14 | |
| tRTP | 8 | |
| tRDWR | 7 | |
| tWRRD | 3 | |
| tWRWR SC | 1 | |
| tWRWR SD | 7 | |
| tWRWR DD | 7 | |
| tRDRD SC | 1 | |
| tRDRD SD | 5 | |
| tRDRD DD | 5 | |
| tCKE | 8 |
| Voltage Block (voltage range) | Min | Rec | Max | BIOS Location: All under Extreme Tweaker |
| DRAM Voltage | 1.34 | 1.35 | 1.36 | |
| SOC Voltage | 0.975 | 1.025 | 1.05 | "CPU SOC Voltage"? |
| cLDO VDDG Voltage | 0.9 | 0.9 | 0.95 | Can't Find |
| cLDO VDDP Voltage | 0.7 | 0.9 | 1.1 |
| Misc Items | Value | BIOS Location |
| Power Down mode | Enabled | Extreme Tweaker > DRAM Timing Control |
| Gear Down mode | Enabled | Extreme Tweaker > DRAM Timing Control |
| Command Rate | 1T | Extreme Tweaker > DRAM Timing Control |
| BGS | Disabled | BankGroupSwap at Advanced > AMD CBS > UMC Common Options > DRAM Memory Mapping |
| BGS alt | Enabled | BankGroupSwap at Advanced > AMD CBS > UMC Common Options > DRAM Memory Mapping |
| FCLK | 1600 | Extreme Tweaker |
| Termination Block Omega | Rec | Alt 1 | Alt 2 | BIOS Location: All under Extreme Tweaker > DRAM Timing Control |
| procODT | 34.3 | 36.9 | 32 | |
| RTT_NOM | OFF | OFF | OFF | |
| RTT_WR | OFF | OFF | OFF | |
| RTT_PARK | RZQ/5(48) | RZQ/5(48) | RZQ/5(48) |
| CAD_BUS Block Omega | Rec | Alt 1 | Alt 2 | BIOS Location: All under Extreme Tweaker > DRAM Timing Control |
| CAD_BUS ClkDrv | 24 | 24 | 24 | "MemCadBusClkDrvStren"? |
| CAD_BUS AddrCmdDrv | 20 | 20 | 24 | "MemCadBusAddrCmdDrvStren"? |
| CAD_BUS CsOdtDrv | 20 | 24 | 24 | "MemCadBusCsOdtDrvStren"? |
| CAD_BUS CkeDrv | 24 | 24 | 24 | "MemCadBusCkeDrvStren"? |
| Main Voltages | Rec | Alt | BIOS Location: All under Extreme Tweaker > Tweaker's Paradise |
| VTT DDR Voltage min | 0.673 | 0.678 | No min/max field |
| VTT DDR Voltage max | 0.6765 | 0.6815 | No min/max field |
| Boot DRAM Voltage | 1.350 | 1.360 | Can't Find |
| Vref (CHA/CHB) | 0.675 | 0.7425 | DRAM Ctrl Ref Voltage on [ChA/ChB] at Extreme Tweaker > Tweaker’s Paradise |
| Debug Voltages | Rec | Alt 1 | Alt 2 | BIOS Location: All under Extreme Tweaker > Tweaker's Paradise |
| VDDP Voltage | 900 | 855 | 815 | |
| VPP Voltage | 2.5 | 2.48 | 2.525 | "VPP_MEM Voltage"? |
| PLL Voltage | 1.8 | 1.77 | 1.83 | "PLL reference voltage" or "1.8V PLL Voltage" under Extreme Tweaker? |
| CAD_BUS Timings | Rec | Alt | BIOS Location: All under Extreme Tweaker > DRAM Timing Control |
| CAD_BUS AddrCmd | 0 | 53 | "MemAddrCmdSetup"? |
| CAD_BUS CsOdt | 0 | 53 | "MemCsOdtSetup"? |
| CAD_BUS Cke | 0 | 53 | "MemCkeSetup"? |
| Memory Interleaving + Tweaks | Value | BIOS Location |
| Memory Interleaving Size | 2 | Advanced > AMD CBS > DF Common Options > Memory Addressing |
| Memory Interleaving | Channel | Advanced > AMD CBS > DF Common Options > Memory Addressing |
| Channel Interleaving Hash | Enabled | Can't Find |
| DRAM R1-R4 Tune | 0/63 | Extreme Tweaker > Tweaker's Paradise |
| L1 Stream HW Prefetcher | Enabled | Advanced > AMD CBS > CPU Common Options > Prefetcher |
| L2 Stream HW Prefetcher | Enabled | Advanced > AMD CBS > CPU Common Options > Prefetcher |
| Super I/O Clock Skew | Disabled | Can't Find |
| Opcache | Enabled | Can't Find |
| Spread Spectrum | Enabled | "VRM Spread Spectrum" under Extreme Tweaker > External Digi+ Power Control or "SB Clock Spread Spectrum" in unknown location (found with F9)? |
| Memory Clear | Disabled | Advanced > AMD CBS > DF Common Options |
| PMU Training | Value | BIOS Location: All under Advanced > AMD CBS > DDR4 Common Options > Phy Configuration > PMU Training |
| DFE Read Training | Enabled | |
| FFE Write Training | Enabled | |
| PMU Pattern Bits Control | Manual | |
| PMU Pattern Bits | A or 10 | |
| MR6VrefDQ Control | Auto | |
| CPU Vref Training Seed Control | Auto |
| CPU/VDDSOC/DRAM | Best DRAM Stability | For CPU too | BIOS Location: All under Extreme Tweaker > External Digi+ Power Control |
| CPU Load-Line Calibration | Level 2/3 | Level 3/4 | |
| CPU Current Capability | 110-130% | 130-140% | |
| CPU VRM Switching Frequency | Manual | Same as for DRAM | |
| Voltage Frequency | 200/300 | 300/400 | |
| CPU Power Duty Control | T.Probe | Same as for DRAM | |
| CPU Power Phase Control | Power Phase Response | Same as for DRAM | |
| CPU Power Thermal Control | 120 | Same as for DRAM | |
| Manual Adjustment | Regular | Ultra Fast | |
| VDDSOC Load-Line Calibration | Level 2/3 | Same as for DRAM | |
| VDDSOC Current Capability | 120.00% | Same as for DRAM | |
| VDDSOC Switching Frequency | Manual | Same as for DRAM | |
| Switching Frequency (Fixed) (KHz) | 300/400 | Same as for DRAM | |
| Phase Control | Manual/Optimized | Same as for DRAM | |
| DRAM Current Capability | 100.00% | 120.00% | |
| DRAM Power Phase Control | Extreme | Same as for DRAM | |
| DRAM Switching Frequency | Manual | Same as for DRAM | |
| Switching Frequency (Fixed) (KHz) | 300/400 | Same as for DRAM |
11-20-2019 04:51 PM
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11-22-2019 06:51 AM