07-05-2016 09:09 AM - last edited on 03-06-2024 02:03 AM by ROGBot
DRAM Voltage 1.65v
DRAM CTRL REF Voltage 0.5 (1.65 * 0.5 = 0.825v)
DRAM CTRL REF Voltage on CHA 0.5 (1.65 * 0.5 = 0.825v)
DRAM CTRL REF Voltage on CHB 0.5 (1.65 * 0.5 = 0.825v)
DRAM Frequency = 1600 Mhz (1866+ no bandwidth gain on H97M-E)
Primary Timings
CAS# Latency 7 (6 = No POST)
RAS# to CAS# Delay 9 (8 = Memtest86+ errors)
RAS# PRE Time 9 (8 = Memtest86+ errors)
RAS# ACT Time 21 (20 = No POST)
Command Rate 1
Secondary Timings
RAS to RAS Delay 4 (Auto, and it should be the minimum)
REF Cycle Time 140 (139 = Memtest86+ errors)
Refresh Interval 65535 (Max. Allowed and still 100% stable, Wat???)
WRITE Recovery Time 12 (9 = No POST; 10 = Memtest86+ errors; 11 = No POST)
READ to PRE Time 4 (Auto, and it should be the minimum)
FOUR ACT WIN Time 16 (15 = No POST)
WRITE to READ Delay 4 (Auto, and it should be the minimum)
CKE Minimum Pulse Width 4 (Auto, and it should be the minimum)
CAS# Write Latency 5 (7/8 Should be, CAS# - 3 minimum possible but no POST -> 5 Stable)
Third Timings
tRDRD 4 (Auto, and it should be the minimum)
tRDRD_dr 6 (Auto, 5 = No POST)
tRDRD_dd 6 (Auto, 5 = No POST)
tWRRD 13 (12 = Memtest86+ errors)
tWRRD_dr 4 (Auto, and it should be the minimum)
tWRRD_dd 4 (Auto suggested 5)
tWRWR 4 (Auto, and it should be the minimum)
tWRWR_dr 6 (Auto suggested 7)
tWRWR_dd 6 (Auto suggested 7)
Dec_WRD 0
tRDWR 9 (Auto, 8 = No POST or POST + Memtest86+ errors)
tRDWR_dr 9 (Auto, 8 = No POST or POST + Memtest86+ errors)
tRDWR_dd 9 (Auto, 8 = No POST or POST + Memtest86+ errors)
Misc.
MRC FastBoot "Disabled"
DRAM CLK Period 3 (2 = Memtest86+ errors)
Channel A DIMM Control "Disable DIMM1" (Only DIMM0 used)
Channel B DIMM Control "Disable DIMM1" (Only DIMM0 used)
Scramble Settings "Optimized (ASUS)"
MCH Full Check "Enabled"
07-12-2016 05:12 AM