- last edited on by
ROGBot
Hello,
I'm measuring the BCLK of the Ryzen 3950X using its Core TSC
( an algorithm of two instructions RDTSCP elapsed by one second )
Results are 99.8 MHz on any Core, which is lower than the Processor factory 100 MHz.
After refining my TSC measurements by removing the inherent cycles of RDTSCP, setting the P-State to a fixed ratio, and all possible programming improvements; I'm still getting a estimated Base Clock of 99.8 MHz.
Thus I have questioned the BIOS and I went into the UEFI settings to change the BCLK from 100 to 100.0625 MHz (the first step above 100) ; save, reboot, and measure the TSC to get a coherent frequency of Cores at ~ 3502.2 MHz (35 * 100.0625)
Next, I changed back into UEFI the BCLK from 100.0625 to 100.0 MHz ; save and went straight into measurements to get an almost perfect Cores frequency of 3500 MHz :cool:
Unfortunately, the following boots restored the BCLK to an estimation of 99.8 MHz :mad:
Question is how to manage the BIOS to retain the willing Base Clock of 100 MHz ?
I'm measuring the BCLK of the Ryzen 3950X using its Core TSC
( an algorithm of two instructions RDTSCP elapsed by one second )
Results are 99.8 MHz on any Core, which is lower than the Processor factory 100 MHz.
After refining my TSC measurements by removing the inherent cycles of RDTSCP, setting the P-State to a fixed ratio, and all possible programming improvements; I'm still getting a estimated Base Clock of 99.8 MHz.
Thus I have questioned the BIOS and I went into the UEFI settings to change the BCLK from 100 to 100.0625 MHz (the first step above 100) ; save, reboot, and measure the TSC to get a coherent frequency of Cores at ~ 3502.2 MHz (35 * 100.0625)
Next, I changed back into UEFI the BCLK from 100.0625 to 100.0 MHz ; save and went straight into measurements to get an almost perfect Cores frequency of 3500 MHz :cool:
Unfortunately, the following boots restored the BCLK to an estimation of 99.8 MHz :mad:
Question is how to manage the BIOS to retain the willing Base Clock of 100 MHz ?
Disabling SPREAD SPECTRUM has solved the issue. I did it on VRM and SB and now my BCLK perfectly reports 99.9 - 100 MHz
CoreFreq monitoring at github.com/cyring/CoreFreq
CoreFreq monitoring at github.com/cyring/CoreFreq
