HI Matthew,
This is a complicated question to answer as it requires a deeper understanding of how clock domains tie together than many of us have.
In the older architectures QPI was used to tie pretty much everything external to the CPU - it was the lone transport mechanism for data from PCIe and the other areas of the system. This is no longer the case on the newer architectures, the PCIe bus is now internal while the DMI link is used for PCH transfer (or anything else its tied to). These domains are tied to the ring bus which is internal in the CPU (you can control ring bus frequency but not DMI by use of multiplier ratios).
There is some DMI control available I guess via BCLK, but the range is limited: either because the speed of communication is already as fast as the buffer can handle or there are limitations on what the external transceivers/layout allows.
Bottom line is, we really dont need control of DMI per se to the extent you've confused with QPI. While overclockable DMI would be nice, the data rates are likely more limited by the bandwidth available on SATA or USB before this becomes a bottleneck. Further, full async control also requires additional logic (transistors etc) to be built into the architecture, which can increase power consumption, complexity and at times introduce latency penalties in other or associated areas.
-Raja
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