Overclocking Using Offset Mode for CPU Core Voltage

[X-ROG]

http://rog.asus.com/51092012/guides/overclocking-using-offset-mode-for-cpu-core-voltage/

:cool:

[rexbinary]

When OCing, I find my voltage using manual mode. Once I am satisifed with it, I convert it to offset. (VID - Vcore = Offset) This seems to work great.

[mapesdhs]

Yes, that's my plan; I've done it before with a friend's P8Z68-V, and my Maximus IV, but I wanted to know if
there was anything unique to X79 systems which was worth knowing. I think I have enough to go on now though.

Ian.

[dazza888]

Is there any way to offset turbo voltage without changing idle voltage? My 2600k will only run 4.6GHz at 1.448V with 1.064V at idle. If I offset at all I get
BSOD at idle because there is not enough V. I tried lowering LLC (which I only have set at 50% now) and it made no difference to my voltages.

[Raja]

You need adaptive mode which these older CPUs do not have unfortunately.

[dazza888]

Raja@ASUS wrote:
You need adaptive mode which these older CPUs do not have unfortunately.

THANKS. I seem to be stable now in offset mode. 4600 with a max voltage of 1.384 and idle at 1.064. For some reason my LLC is at 0% now and it's running fine with the max voltage right where I wanted it.

[joesaiditstrue]

Is it true that using offset voltage can cause errors/bios instability in the Maximus V Extreme, specifically with the management engine? I've always previously used offset rather than manual voltage and had to return a board two or three times due to "ME Version: N/A" and read somewhere that it could be tied to using Offset voltage control

[ajc9988]

@raja@asus - Question: When, if it is possible through the bios, will Asus separate the voltage offset from effecting C-states other than C0?

The primary problem with voltage offset is that it automatically offsets all C-state values by the same amount as C0 for load conditions. If there is a way to separate the C0 voltage offset from all other C-states, whether by pegging all other C-states to a static voltage or individually calibrating (or allowing the customer to individually calibrate) the voltage offset for each lower C-state (C1-C7 on the 4790K), wouldn't this prevent the boot problems, remove the problem of enabling Adaptive for voltage offset OC when it provides too much voltage to the Vcore, and allow for a lower offset than that possible by static pegging of voltage for C0? It seems that this is the simpler, more elegant answer than adaptive (although, admittedly, may cause a major bios rewrite to separate the varying voltages of C-states and the voltage offset of C0). I believe this would expedite the adoption of voltage offset while utilizing Haswell and future processors additional C-states for lower energy consumption.

joesaiditstrue wrote:
Is it true that using offset voltage can cause errors/bios instability in the Maximus V Extreme, specifically with the management engine? I've always previously used offset rather than manual voltage and had to return a board two or three times due to "ME Version: N/A" and read somewhere that it could be tied to using Offset voltage control

This isn't true. Read my post. By doing voltage offset, you can do a negative offset that affects a lower C-state for idle voltage. Because it makes this voltage too low to operate at that frequency, it causes stability issues. Not problems with the ME!

[Raja]

The control parameters for all of these situations are coded and developed by Intel not ASUS. The control you have right now is what they offer us. There are no separate voltage entries for individual C-States that I am aware of. The C-States only control the depth of power gating across the die - so there is no inherent reason for Intel to provide additional VID points for them.

[ajc9988]

Thank you for the information! Very enlightening! So the current issue is with Intel's current solution, not the BIOS. Tells me where to make future requests for product features on K and X series processors. I agree that, generally, there is no inherent reason for Intel to provide additional VID points for them. But, in light of solutions for enthusiasts, this is something that can be requested. Once again, thank you for the information!

EDIT:

@Raja@asus - Would there be a way that Asus, as an Intel partner, make a request for something similar to this to better facilitate Dynamic Voltage Offset overclocking? I have sent a request yesterday, but coming from a larger corporation watching out for their products gets more attention than a single end-consumer. Also, it could change and evolve future Asus ROG offerings in a positive manner! This would only need to apply to K and X series processors. It would be nice if it could apply to the current Haswell processors, but if it can only be incorporated in the future, that would be acceptable. This would remove the largest limitation of DVO (Dynamic Voltage Offset) and bios voltage offset that currently exists (as well as providing potentially more headroom for laptop OC offerings from Asus).

[Raja]

I'm not sure I understand the request really. When the processor is under load, the core/cores under load are not in C-state. With that in mind, the voltage required for the load state would be identical regardless of which C-State the processor or cache exited before going in to load state (some caveats in number one below).

Outside that (let me clear this up as much as I can for you):

1) Most enthusiasts do not bother with single core clocking - and the new OSes don't really isolate single cores either. The OSes are set up to load balance - so there isn't much disparity. Even if you were clocking only a single core, the change in VID would not be that large really - depends on internal power plane losses vs current loads and I can;t imagine those would be "huge".

2) When the processor is power gated, changing VID levels does not affect power consumption very much because the sections that are gated are not drawing sufficient current.

3) Each C-State has a hold time associated between idle and the processor going in to load state. The deeper the C-State, the greater the hold time before the processor can begin dealing with the load. The hold time allows sufficient time for the power gated sections to exit low power mode and for VCC to settle at/around the target VID.

4) I suspect the issue you are concerning yourself with is how offset affects the entire VID stack. This isn't related to the C-states themselves per se. It's related to offset voltage shifting the entire VID stack.

5) The POST issue with Haswell and some PSUs was related to the amount of current drawn at the rail. When power gated, the current level isn't going to change much with VID - so the POST issue would still occur even if the base VID were to be moved.

6) Any BOOT issues that occur happen when the processor is in load state - so applying different C-State VIDs is not the answer to those either. The user will need to apply sufficient offset or adaptive voltage to ensure that VCC is sufficient for the ratio (core frequency) being applied.


In order to get any traction to your personal request to Intel - make sure you acquaint yourself firmly with what the C-states do. Then work out if the request is feasible. Otherwise I can't see this going anywhere assuming it makes it to a chip engineer.

Good Luck!