02-17-2014 12:52 PM - last edited on 03-05-2024 11:39 PM by ROGBot
02-21-2014 07:39 AM
LaserPete wrote:
Thanks for joining in Coldstatic,
With answers come more questions.
To start with I'm running 3900 MHz in Turbo mode at 100% through Windows 7, fixed. BIOS is 1302.
I'm using 32 GB's of RAM at 2133 MHz XMP.
I've left Hyper Threading on for now, might like to use it later.
I added .302v to System Agent, 0.848v to 1.15v. The OS doesn't freeze or give BSOD's during logins now, so far that is. Thanks Nate!
Some of the question I have,
Do any of these voltages scale with load or frequency?
When you mention voltages like; .100, .150, .200, etc. are you refering to entering offsets?
Where do these voltage calculations come from and do they take into account different memory setups?
Whats the best software to use for memory stablity tests? I have been using OCCT Linpack 64bit, all cores, AVX off. It never detected a problem.
I want to make the memory stable at XMP first before I start to OC. My target OC is a modest 4.2 GHz but it would be fun to see what it could do. I will drop the memory to 1333 MHz when I start OCing though. I also would like to use adaptive mode (Turbo mode?) to reduce heat at load and frequency idle.
Any help is appreciated since I'm quite new to this.
Thanks,
Pete
ASUS Maximus VI Extreme
Intel i7-4770K
G-Skill 32-GB 2133 MHz, C11
Samsung 840 Pro 256GB - X2
WD 1TB Black
EVGA GTX-780 Ti SC w/ACX
EVGA SuperNOVA 1000 P2 PS
Corsair H110 cooler
Corsair 650D case
Windows 7 Pro 64
Raja@ASUS wrote:
The voltage to the System agent does not impact performance in this way, so you're looking at the wrong thing here Coldstatic. The voltage helps with stability as it supplies the IO transceivers - higher voltage can help reach required slew rates (acceleration) for faster switching frequencies.
The PCH communicates with the processor via the DMI bus - likely DC coupled with the PCH side being supplied from the PCH core voltage and the DMI transceivers on the CPU side tied to one of the rails (SA, IO or VTT etc). Either way, performance should not really change to any appreciable degree simply by manipulating the IO rail voltages.
I could post some suppositions about error margins and the buffers (crudely related to required slew rates having a small change in a benchmark score) - but I'd rather not go down that route on a forum as it would not mean a thing in terms of accurate information (I'm not even sure such fail-safes are part of the design).
The performance hit you're experiencing is simply due to you lowering the cache ratio and possibly DRAM divider (if IRST drivers are used as they reserve memory as cache) to reach a higher CPU clock. The DMI bus will communicate with the CPU via the ring ratio - so lowering the ring ratio speed will impact the DMI perf to some degree.
On the M6E there's a nifty trick to help with BCLK that can impact DMI, but that only ties in to BCLK ranges and not the type of OCing you're eluding to above.
Raja@ASUS wrote:
Memory training is performed during pre-POST. As memory stability is reliant on the right level of VCCSA and IO-D, any instability during the training process will extend POST time because the IMC will re-attempt to train the DIMMs if they are not fully stable (if they continue to be unstable the board will halt with a memory training or IMC related error code).
Friendly note: May I suggest you break up long posts a bit more with paragraphs, as it makes reading them difficult 😛
PS: If your UEFI version has "source clock tuner" try using different values and comparing PCH performance.
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