That memory likely uses ICs that are of older type. It may not work well with the memory controller on the newer CPUs without a lot of adjustment.
Memory is binned on the platforms that are current at the time it is released. If there are any changes in memory controller signal integrity or the level of data a newer architecture is able to transfer over the bus in a given time frame, it may violate the capabilities of the memory kit to run the frequency. For the latter point, I am referring to improvements in efficiency, where newer processors are able to transfer more data than the kit was binned for.
Changes in the capabilities of the transceivers used in the processors and the associated board impedance play a part from a signal integrity perspective - it could be that the ICs used on some older memory kits are not easy to swing voltage into. In such cases, it is difficult to get the kits stable at their rated frequency or timings ithout relaxing the timings and increasing voltages.
If the XMP settings do not work, you will have to experiment by increasing some of the timings in the DRAM timing pages by +2 clocks. If that does not work you may need to increase VCC IO-D as well. If the latter does not help either, then you will have to accept running the memory kit at a lower operating frequency.
-Raja
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