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The Maximus IV Gene-Z is the smaller sibling to the flagship Maximus IV Extreme and Maximus IV Extreme-Z motherboards. Many of the overclocking features found on the bigger siblings make their way onto the Gene-Z.
We’ve also managed to provide you with a 250 amp capable VRM on the Gene-Z to supply CPU Vcore. That means the Gene-Z should be capable of keeping up with its full sized ATX counterparts when it comes to processor overclocking!
We’re going to walk you through key BIOS overclocking features and break down their usage, to help you get the most from this exciting little motherboard.
Upon entering UEFI BIOS, we navigate to the AI Tweaker menu:
CPU Level Up: Allows us to select a pre-set profile that contains voltage and bus adjustments to apply a mild overclock to the system. Use this setting if you do not wish to overclock the system manually.
Load Extreme OC Profile: For extreme overclocking only. Contains a pre-set that sets all processor and system current thresholds to maximum – in order to facilitate quick setup when overclocking the processor under sub-zero cooling.
Ai Overclock Tuner: Options are Auto, Manual and X.M.P.
Auto: This is the default setting, and needs to be changed to Manual if you wish to change BCLK (BCLK is the base reference frequency from which processor and other system bus frequencies are derived).
X.M.P: Extreme memory profile, use this option if you have Sandy Bridge qualified XMP memory. X.M.P. profiles contain pre-sets for system buses and in some cases voltages. If the specified speed of the DIMMs is greater than the supported memory frequency of the platform, a platform specific X.M.P. profile option becomes mandatory because processor core and memory controller voltage requirements vary from architecture to architecture. High-speed enthusiast memory kits manufactured before the inception of the Sandybridge platform may not contain the necessary/adequate voltage offset settings for the system to be completely stable. In such instances, manual adjustments of memory controller voltage and memory timings may be necessary.
Selecting the X.M.P setting opens up options for X.M.P profile selection (the kit may contain more than one X.M.P profile), and also opens up the BCLK option for changing system bus frequency. Note that memory operating frequency and maximum CPU operating frequency are shown towards the top of the Ai Tweaker menu, while memory timings and voltage are displayed next to the XMP profile selection box.
BCLK/PCIe Frequency: This function becomes available if X.M.P or Ai Overclock Tuner “Manual” are selected. The base BCLK frequency is 100MHz. As the name implies, changing the BCLK frequency will also change PCIe frequency. The maximum CPU core frequency is derived via multiplication with the Turbo Ratio setting (final frequency is displayed at the top-left of the Ai Tweaker menu).
Bear in mind that the adjustment margin for this setting is not large - most processors have a range from 95~107 MHz. Changes to BCLK and stable operation of high memory frequencies (DDR3-2133+ for example) may benefit from manipulation of clock skew settings (more on that subject later in the guide).
Turbo Ratio: Options are “Auto”, “By All Cores” and “By Per Core”. A description of these settings is provided in the right-hand column of the UEFI BIOS and can be seen when the Turbo Ratio setting is selected.
By All Cores: This sets the CPU core frequency multiplier; multiplied by BCLK to give the target CPU frequency (under full load conditions if SpeedStep is active). “Auto”: Stock CPU multiplier Ratio used. Manual numerical entry of the desired Turbo Ratio is accepted.
Per Core: Allows setting the maximum Turbo multiplier of each physical processor core.
The available multiplier range is limited by both processor model and the ability of each CPU.
Internal PLL Overvoltage: Options are “Auto”, “Disabled” and “Enabled”. A manual setting of “Disabled” is recommended within the bounds of moderate overclocking. Using Core frequency multipliers in excess of 45X may need a setting of “Enabled”. The requirements of the “Enabled” setting will vary from processor to processor. The unfortunate side-effect is that resume from S3 sleep states is not possible when Internal PLL Overvoltage is set to “Enabled” - this is a hardware limitation, and only fixable by Intel.
Memory Frequency: “Auto” will automatically select a memory multiplier ratio according to memory module SPD (Serial Presence Detect). Manual selection of the available memory frequency multiplier ratios is possible and works according to the abilities of the DRAM and processor. Granular control of memory frequency is available by manipulating BCLK (within functional limits).
Memory Bandwidth Booster: Uses a tighter set of memory timings for benchmarking purposes. Use only with enthusiast oriented memory kits. Keep disabled when using 4GB DIMMs or when gunning for maximum memory frequency.
iGPU Max Frequency: Sets the maximum iGPU frequency in 50MHz steps (implied).
EPU Power Saving Mode: When “Enabled” is selected, utilizes power phase management based upon system loading to reduce system power consumption. A setting of “Disabled” is recommended for heavy overclocking.
We’ve also managed to provide you with a 250 amp capable VRM on the Gene-Z to supply CPU Vcore. That means the Gene-Z should be capable of keeping up with its full sized ATX counterparts when it comes to processor overclocking!
We’re going to walk you through key BIOS overclocking features and break down their usage, to help you get the most from this exciting little motherboard.
Upon entering UEFI BIOS, we navigate to the AI Tweaker menu:
CPU Level Up: Allows us to select a pre-set profile that contains voltage and bus adjustments to apply a mild overclock to the system. Use this setting if you do not wish to overclock the system manually.
Load Extreme OC Profile: For extreme overclocking only. Contains a pre-set that sets all processor and system current thresholds to maximum – in order to facilitate quick setup when overclocking the processor under sub-zero cooling.
Ai Overclock Tuner: Options are Auto, Manual and X.M.P.
Auto: This is the default setting, and needs to be changed to Manual if you wish to change BCLK (BCLK is the base reference frequency from which processor and other system bus frequencies are derived).
X.M.P: Extreme memory profile, use this option if you have Sandy Bridge qualified XMP memory. X.M.P. profiles contain pre-sets for system buses and in some cases voltages. If the specified speed of the DIMMs is greater than the supported memory frequency of the platform, a platform specific X.M.P. profile option becomes mandatory because processor core and memory controller voltage requirements vary from architecture to architecture. High-speed enthusiast memory kits manufactured before the inception of the Sandybridge platform may not contain the necessary/adequate voltage offset settings for the system to be completely stable. In such instances, manual adjustments of memory controller voltage and memory timings may be necessary.
Selecting the X.M.P setting opens up options for X.M.P profile selection (the kit may contain more than one X.M.P profile), and also opens up the BCLK option for changing system bus frequency. Note that memory operating frequency and maximum CPU operating frequency are shown towards the top of the Ai Tweaker menu, while memory timings and voltage are displayed next to the XMP profile selection box.
BCLK/PCIe Frequency: This function becomes available if X.M.P or Ai Overclock Tuner “Manual” are selected. The base BCLK frequency is 100MHz. As the name implies, changing the BCLK frequency will also change PCIe frequency. The maximum CPU core frequency is derived via multiplication with the Turbo Ratio setting (final frequency is displayed at the top-left of the Ai Tweaker menu).
Bear in mind that the adjustment margin for this setting is not large - most processors have a range from 95~107 MHz. Changes to BCLK and stable operation of high memory frequencies (DDR3-2133+ for example) may benefit from manipulation of clock skew settings (more on that subject later in the guide).
Turbo Ratio: Options are “Auto”, “By All Cores” and “By Per Core”. A description of these settings is provided in the right-hand column of the UEFI BIOS and can be seen when the Turbo Ratio setting is selected.
By All Cores: This sets the CPU core frequency multiplier; multiplied by BCLK to give the target CPU frequency (under full load conditions if SpeedStep is active). “Auto”: Stock CPU multiplier Ratio used. Manual numerical entry of the desired Turbo Ratio is accepted.
Per Core: Allows setting the maximum Turbo multiplier of each physical processor core.
The available multiplier range is limited by both processor model and the ability of each CPU.
Internal PLL Overvoltage: Options are “Auto”, “Disabled” and “Enabled”. A manual setting of “Disabled” is recommended within the bounds of moderate overclocking. Using Core frequency multipliers in excess of 45X may need a setting of “Enabled”. The requirements of the “Enabled” setting will vary from processor to processor. The unfortunate side-effect is that resume from S3 sleep states is not possible when Internal PLL Overvoltage is set to “Enabled” - this is a hardware limitation, and only fixable by Intel.
Memory Frequency: “Auto” will automatically select a memory multiplier ratio according to memory module SPD (Serial Presence Detect). Manual selection of the available memory frequency multiplier ratios is possible and works according to the abilities of the DRAM and processor. Granular control of memory frequency is available by manipulating BCLK (within functional limits).
Memory Bandwidth Booster: Uses a tighter set of memory timings for benchmarking purposes. Use only with enthusiast oriented memory kits. Keep disabled when using 4GB DIMMs or when gunning for maximum memory frequency.
iGPU Max Frequency: Sets the maximum iGPU frequency in 50MHz steps (implied).
EPU Power Saving Mode: When “Enabled” is selected, utilizes power phase management based upon system loading to reduce system power consumption. A setting of “Disabled” is recommended for heavy overclocking.
DRAM Timing Control: Takes us to the DRAM timing sub-menu, where all primary, secondary and tertiary memory timings can be set:
Mem-Tweakit Support: Can be left Enabled at all times. This setting allows manipulation of DRAM timings from the operating system in real-time using the ASUS Mem-Tweakit software.
Memory timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to make manual adjustments, the primary settings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, VCCIO and to a lesser extent CPU Core Voltage may be necessary to facilitate tighter timings.
Primary Timings
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP.Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD - although the impact does increase if multiple page open and close requests are sent to the same memory IC and to a lesser extent rank (there are 8 physical ICs per rank and only one page can be open per IC at a time, making up the total of 8 open pages per rank simultaneously).
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible. If however the banks in a rank have no open pages, and multiple banks need to be opened on that rank or across ranks, the impact of Command Rate increases.
Most DRAM module densities will operate fine with a 1N Command Rate. Memory modules containing older DRAM IC types may however need a 2N Command Rate.
Secondary Timings
DRAM RAS to RAS Delay:Also known as tRRD (activate to activate delay). Specifiesthe number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks.
DRAM Ref Cycle Time: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.
DRAM Refresh Interval: Also known as tREFI. Specifies the period that must elapse in DRAM clocks before a refresh command is issued. A larger value here is actually more aggressive as it increases the delay between refreshes. The charge stored in DRAM cells diminishes over time and must be refreshed to ensure that data is not lost. The minimum interval between refreshes varies according to DRAM ICs and the density of the modules – higher density module generally need refreshing more often (lower value for tREFI). Refresh interval requirements also tend to vary according to DRAM temperature (changes in cell leakage rates) and VDIMM, so be prepared to experiment with values if sub-zero cooling is used on memory.
DRAM Write Recovery Time: Defines the number of clock cycles that must elapse between a memory write operation and a precharge command. Most DRAM configurations will operate with a setting of 10 clocks up to DDR3-1866. After that, relaxing to 12+ clocks may be necessary at DDR3-2000+. High performance PSC type DIMMs can use a tWR of 8 at speeds over DDR3-2300 (memory controller permitting).
DRAM Read to Precharge Time: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased.
DRAM Four Activate Window: Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum value for tFAW at the chipset level is 16 DRAM clocks.
As the effects of tFAW spacing are only realised after four Activates to the same DIMM, the overall performance impact of tFAW is not large, however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value.
As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks).
DRAM Write to Read Delay: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks. As with tRTP this value may need to be increased according to memory density and memory frequency.
DRAM CKE Minimum Pulse Width: Also known as tCKE. Specifies the minimum time in DRAM clock cycles the DRAM stays in self-refresh mode (low power state) or in clock enabled state (normal operation) before assertion or de-assertion. Toggling of CKE is initiated with C-States and DRAM power saving modes active only and can safely be left at default value for all operating conditions.
Mem-Tweakit Support: Can be left Enabled at all times. This setting allows manipulation of DRAM timings from the operating system in real-time using the ASUS Mem-Tweakit software.
Memory timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to make manual adjustments, the primary settings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, VCCIO and to a lesser extent CPU Core Voltage may be necessary to facilitate tighter timings.
Primary Timings
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP.Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD - although the impact does increase if multiple page open and close requests are sent to the same memory IC and to a lesser extent rank (there are 8 physical ICs per rank and only one page can be open per IC at a time, making up the total of 8 open pages per rank simultaneously).
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible. If however the banks in a rank have no open pages, and multiple banks need to be opened on that rank or across ranks, the impact of Command Rate increases.
Most DRAM module densities will operate fine with a 1N Command Rate. Memory modules containing older DRAM IC types may however need a 2N Command Rate.
Secondary Timings
DRAM RAS to RAS Delay:Also known as tRRD (activate to activate delay). Specifiesthe number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks.
DRAM Ref Cycle Time: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.
DRAM Refresh Interval: Also known as tREFI. Specifies the period that must elapse in DRAM clocks before a refresh command is issued. A larger value here is actually more aggressive as it increases the delay between refreshes. The charge stored in DRAM cells diminishes over time and must be refreshed to ensure that data is not lost. The minimum interval between refreshes varies according to DRAM ICs and the density of the modules – higher density module generally need refreshing more often (lower value for tREFI). Refresh interval requirements also tend to vary according to DRAM temperature (changes in cell leakage rates) and VDIMM, so be prepared to experiment with values if sub-zero cooling is used on memory.
DRAM Write Recovery Time: Defines the number of clock cycles that must elapse between a memory write operation and a precharge command. Most DRAM configurations will operate with a setting of 10 clocks up to DDR3-1866. After that, relaxing to 12+ clocks may be necessary at DDR3-2000+. High performance PSC type DIMMs can use a tWR of 8 at speeds over DDR3-2300 (memory controller permitting).
DRAM Read to Precharge Time: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased.
DRAM Four Activate Window: Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum value for tFAW at the chipset level is 16 DRAM clocks.
As the effects of tFAW spacing are only realised after four Activates to the same DIMM, the overall performance impact of tFAW is not large, however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value.
As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks).
DRAM Write to Read Delay: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks. As with tRTP this value may need to be increased according to memory density and memory frequency.
DRAM CKE Minimum Pulse Width: Also known as tCKE. Specifies the minimum time in DRAM clock cycles the DRAM stays in self-refresh mode (low power state) or in clock enabled state (normal operation) before assertion or de-assertion. Toggling of CKE is initiated with C-States and DRAM power saving modes active only and can safely be left at default value for all operating conditions.
DRAM CAS Write Latency: Also known as CWL. Sets the column write latency timing for write operations to DRAM. For most purposes the minimum value should be equal to read CAS, as the timing constraints of accessing a column are the same. This timing is just as important as read CAS because data has to be written to DIMMs in order to be read.
DRAM RTL: Also known Round Trip Latency. RTL denotes the number of clock cycles it takes for a data to arrive at the memory controller after a read CAS command is issued. This value is specified in memory controller clock cycles (not DRAM clock cycles). On the Sandybridge architecture these values can safely be left on AUTO most of the time and do not need manual adjustment.
Third Timings
Most of these timings can be left on AUTO unless tweaking for SuperPi 32M
tWRDR (DD): Sets the delay period between a write command that is followed by a read command; where the read command requires the access of data from a different rank or DIMM. A value of 1 clock is possible on high performance memory. For higher density modules this value may need relaxing to 2~4 clocks as memory frequency is increased.
tRWDR (DD): Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank or DIMM. A setting of 3 clocks suits most DIMM configurations all the way to DDR3-2133. Relax only if you are experiencing stability issues when running in excess of 8GB of memory.
tRWSR: Sets the read to write delay timing where the write follows a read on the same rank. Can be left to 3 clocks for most configurations. 1~2 clocks may be possible at lower memory frequencies depending upon module density (sub DDR3-1866).
tRR(DD): Sets the read to read delay where the subsequent read requires the access of a different DIMM. 3 clocks will work with most configurations.
tRR(DR): Sets the read to read delay where the subsequent read requires the access of a different rank on the same DIMM. 3 clocks will work with most configurations at high memory frequencies. Only needs adjustment when double-sided DIMMs are used.
tRR(SR): Sets the read to read delay where the subsequent read accesses a different bank on the same rank. On the face of it the function of this timing seems akin to tRRD. We are not sure on its real usage scenario though suspect as both timings are included; this might be spacing where the page to be accessed is already open on a different bank is already open. The minimum internal spacing is 4 DRAM clocks.
tWW(DD): Sets the write to write delay where the subsequent write requires the access of a different DIMM. 3 clocks will work with most configurations.
tWW(DR): Sets the write to write delay where the subsequent write command requires the access of a different rank on the same DIMM.
tWWSR: Sets the write to write delay where the subsequent write command requires the access of a different bank on the same rank.
DRAM IO-L & RTL Offset: Sets a delay in the IMC receive schedule to account for IO delay variance in the arrival of data for various DIMM types after a read command is issued. These settings can safely be left at Auto unless you see Channel B offset by a lower value than Channel A (an equal value works fine). If Channel B drifts to a lower value then delay Channel B by one clock. Upon re-POST this should equalize the channel offset. Monitor again upon subsequent reboots, and remove the additive delay if need be.
The memory most susceptible to this drift is Elpida Hyper. At speeds over DDR3-2000, Hyper IC modules will not be stable if the Channel B offset is anything other than two clocks.
GPU.DIMM Post: opens a sub-page which shows how many GPUs are inserted into the PCIe slots and how many DIMMs are being used. If there are any peripheral issues or system bus speeds have been increased too far, one of the GPUs or memory modules may not show in the GPU DIMM Post screen – a quick glance here can save a lot of head-scratching.
VCore PWM Mode: Sets the conditions for load balancing across phases. “T.Probe” monitors phase thermal conditions and balances load accordingly. “Extreme” balances the current load across all FETs irrespective of thermal conditions.
VCore MOS volt. Control: Sets the CPU VRM driver output voltage. This setting can be left on Auto for all overclocking.
VCore Load-Line Calibration: Sets a margin between idle and full processor load voltage to compensate for overshoot. To clarify; overshoot is a short duration (Intel specification stipulates less than 25 micro-seconds at stock voltages) voltage excursion beyond applied processor Vcore. We recommend a setting of High or Ultra-High for most overclocking.
VCore Switching Freq: Sets the switching frequency of the power FETs supplying processor Vcore. Lower switching frequencies lead to a higher VRM efficiency (small power saving) and lower VRM operating temperatures. Setting a higher switching frequency aids transient response (the recovery of voltage to the applied level after a load condition) – at the expense of heat.
VCore Phase Control: Sets the load dependant phase switching conditions; the VRM is made up of multiple phases (each phase has at least two FETs). During light-load conditions FETs can be switched off to save power. “Standard” and “Optimized” are adequate for most loading conditions. If pushing processors past 4.8GHz, then Extreme or “Manual” with “Ultra-Fast” is recommended.
VCore Over-Current Protection: Increases the power threshold before over-current protection limits power (either by shut-off or throttling). We set this to 140% for all overclocking (processor cooling permitting).
VRM Over-temperature Protection: Monitors CPU VRM MOSFET temperatures and if the temperature breaches a certain threshold either throttles the processor clock frequency to reduce current consumption or shuts-down the motherboard to prevent VRM failure. May be turned off is using sub-zero cooling on the processor. For all other purposes, leave this setting enabled and provide active cooling over the CPU VRM heatsink to keep temperatures in-check.
iGPU Load-line calibration: As Load-line calibration for the CPU but for the integrated graphics processor voltage rail. A value of “Higher” should suffice for most loading requirements.
iGPU Current Capability: As CPU Current Capability but for the iGPU.
VCore EMI Reduction: Modulates the CPU VRM clock signal to reduce the peak magnitude of radiated noise emission levels (may be of use during audio recording/playback from the analogue audio outputs) . This setting should be used at stock system operating parameters only.
VDRAM Switching Freq: As CPU VCore switching frequencybut for the DRAM VRM. Increase the switching frequency when running speeds over DDR3-2000 with 2GB DIMMs (4GB configuration) or when running 4GB modules over DDR3-1866 speeds.
VDRAM Full Phase Control: A setting of Enabled ensures that both DRAM VRM phases remain operational at all times (irrespective of current draw). The Disabled setting allows one phase to be switched off during light loading scenarios to save on system power consumption. For heavy overclocking a setting of Enabled is recommended.
VDRAM Over-Current Protection: A setting of Disabled lifts the current-trip threshold of the VRM. Set Disabled only if benchmarking.
VCCSA/IO Switching Freq: As CPU VCore Switching frequency but for the VCCSA/IO VRM. Increase the switching frequency when running memory speeds over DDR3-2000 with 2GB DIMMs (4GB configuration) or when running 4GB modules over DDR3-1866 speeds.
VCCSA/IO Full Phase Control: A setting of Enabled ensures that all VCCSA/IO VRM phases remain operational at all times (irrespective of current draw). The Disabled setting allows phases to be switched off during light loading scenarios to save on system power consumption. For heavy overclocking a setting of Enabled is recommended.
VCCSA/IO Over-Current Protection: A setting of Disabled lifts the current-trip threshold of the VRM. Set Disabled only if benchmarking.
CPU Voltage: Two options here. The first is “Manual Mode”, which allows us to set a ‘static’ level of voltage for the CPU. The second mode is “Offset Mode”, for which we have covered the usage of here.
iGPU Voltage: As CPU Voltage – “Offset” and “Manual” modes supported.
DRAM Voltage: Sets voltage for DRAM. 1.50V is stock, increase or decrease according to the capabilities of your memory. Memory kits rated at 1.65V or under are recommended for use with
DRAM Data Ref (both A and B): Sets the voltage reference level for DQ sampling. The base AUTO value is set at 50% (the mid-point of the voltage swing) and seldom needs adjustment unless running very high memory frequencies. If experiencing instability when running benchmarks at very high memory and processor frequencies, one step over or under 50% (0.495X or 0.505X) may be required on one or both channels to counter DQS skew issues (especially with Elpida Hyper memory modules when the processor is sub-zero cooled).
DRAM CTRL Vref (both A and B): As above, although the CTRL/CMD lines are not as “busy” as the DQ lines. Base is 50% of VDD (VDIMM). If making adjustments to Data (DQ) reference, then set the corresponding CMD/CTRL for that channel to the same value and see if it helps.
VCCSA/IO Voltage: Sets termination and/or rail voltages for various transceiver stages of the processor. The base setting is 1.05V, and some processors need little adjustment from this value even when overclocking 4GB density memory modules. Processors with weaker memory controllers may require a higher setting (up to 1.20V) to facilitate overclocking. As a general rule, increase or reduce in small steps (0.025V) and check for stability before increasing the voltage, as a voltage level that is too high can also induce instability.
Note that System Agent voltage (VCCSA) is tied to VCCIO on our Z68 boards. SA voltage seldom needs adjustment and tying it to VCCIO seems to cause no discernible adverse effects for overclocking in our testing to date.
CPU PLL Voltage: Sets the voltage for the internal phase locked loop. The role of the PLL is to ensure that the output clock of the internal processor frequency synthesizers maintains phase coherency with the reference clock signal (supplied from a clock generator located within the PCH).
Unlike Nehalem/Gulftown architectures, Sandybridge can benefit from a small increase to PLL voltage when running higher CPU multiplier ratios (hence CPU core frequency). As always, caution is advised with regards to over-voltage on this rail – personally I don’t use any more than 1.85V and that too when processors are sub-zero cooled. Excessive PLL voltage can degrade or kill a processor quicker than overvoltage on any other voltage rail.
PCH Voltage: Platform Controller Hub voltage (PCH is also known as Southbridge). 1.05V or so is base. Needs no adjustment and can be left on AUTO for all types of overclocking. DC coupling of transceiver stages connecting the processor IO stages and PCH may exist, however, in our testing to date the usable over-voltage margin of VCCIO/VCCSA is not large enough to cause adverse effects and does not necessitate ramping of PCH voltage in tandem (up-to 1.20VCCIO/VCCSA tested with 1.05V PCH).
Skew Driving Voltage & BCLK Skew: Shamino wrote up a quick instruction set for optimal tuning of these settings:
First set Skew driving voltage to 1.04v, set BCLK skew to 0 , rest of skew to auto and start pushing BCLK to find limit.
Next set Skew driving voltage to 1.04v, set BCLK skew to -8 , rest of skew to auto and start pushing BCLK to find limit.
Next set Skew driving voltage to 1.04v, set BCLK skew to -12 , rest of skew to auto and start pushing BCLK to find limit.
If BCLK is increasing going to -12 then slowly lower skew driving voltage from 1.04v to try to max BCLK again.
For reducing BCLK First set BCLK skew to 0 , set Skew driving voltage to 1.04v,rest of skew to auto and start reducing BCLK to find limit.
Next set BCLK skew to +12 , set Skew driving voltage to 1.04v,rest of skew to auto and start reducing BCLK to find limit.
If BCLK is reducing going to +12 then slowly increase skew driving voltage from 1.04v to try to reduce BCLK again.
CPU Spread Spectrum: Modulates the processor clock to reduce radiated noise emissions. Disable if overclocking, as clock modulation will increase instability.
Components Used to help test for this guide:
Intel i7-2600K CPU
Corsair HX1200 PSU
Corsair H70 CPU Cooler
Corsair Dominator GT DDR3-2200 8-8-8-24 4GB rev 2.1 Memory Kit
GSkill Flare 8-9-8-24 DDR3-2000 8GB Memory Kit
Big thanks to Corsair and GSkill!:cool:
