These timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to experiment with various timings, the primary settings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, CPU/NB voltage and to a lesser extent CPU Core Voltage may be necessary to facilitate tighter timings. DRAM CAS Latency
: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in almost every read transaction, it is considered to be the most important timing in relation to memory read performance.
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles. DRAM RAS TO CAS Latency
: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory. DRAM RAS# PRE Time
: Also known as tRP. Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD - although the impact does increase if multiple page open and close requests are sent to the same memory IC and to a lesser extent rank (there are 8 physical ICs per rank and only one page can be open per IC at a time, making up the total of 8 open pages per rank simultaneously). DRAM RAS Active Time
: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP. DRAM READ to PRE Time
: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-1866 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 5 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased. DRAM RAS to RAS Delay
: Also known as tRRD (activate to activate delay). Specifies the number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks. A setting of 5 clocks and upwards may be necessary to achieve stability at speeds over DDR3-1866. DRAM Write to Read Delay
: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks. As with tRTP this value may need to be increased according to memory density and memory frequency. DRAM CAS Write Latency
: Also known as CWL. Sets the column write latency timing for write operations to DRAM. For absolute stability the minimum value should be set equal to read CAS, as the timing constraints of accessing a column are the same, although there are some modules that can handle a setting of Read CAS -1 or Read CAS -2 depending upon memory frequency . This timing is just as important as read CAS because data has to be written to DIMMs in order to be read. DRAM Write Recovery Time
: Defines the number of clock cycles that must elapse between a memory write operation and a Precharge command. Most DRAM configurations will operate with a setting of 10 clocks up to DDR3-1866. After that, relaxing to 12+ clocks may be necessary at DDR3-2000+. DRAM Ref Cycle Time
: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh. DRAM Row Cycle Time
: Also known as tRC. Stipulates the number of DRAM clocks that must elapse before another Activate Command (row select) to the same bank. The minimum spacing is tRAS+tRP. Setting a higher value may aid stability somewhat at the chance of a very small performance hit. DRAM READ to WRITE Delay
: Sets the read to write delay timing where the write follows a read on the same rank. A setting of 4 clocks should suffice for most configurations, although some DIMMs may need a higher setting to aid stability as memory frequency is increased past DDR3-1866 at the expense of performance. DRAM WRITE to READ Delay (DD)
: Sets the delay period between a write command that is followed by a read command; where the read command requires the access of data from a different DIMM. A value of 1 clock is possible on high performance memory. For higher density modules this value may need relaxing to 2~4 clocks as memory frequency is increased.