from what ive read on the three full slot vi pcie z87 boards such as the formula, if you put anything into the lower x4 slot, it will make the top two full slots run at x8 x4. is this correct? in other words you cannot run sli + physx? is this also true for the z97 ranger/hero? is sli+physx only available for the maximus vi extreme z87 (and rampage black) ?
That's correct. When anything is detected in the lower x4 slot, the four lanes are stolen from the second socket giving x8x4x4. The eight lanes for the second socket are stolen from the first -- the x8x8 condition.
The limitation on PCIE3 lanes that causes the 8/4/4 split is in the CPU, not the X87/z97. The Haswell CPUs have had a 16 lane limit. I think that same limit is expected for the Haswell Refresh CPUs that will use the z97.
The M6E uses an external Plex chip -- a lane switch that time shares the 16 CPU lanes to serve 4 sockets.
Extreme Edition processors that use the 2011-pin socket on the Rampage boards have 40 PCIE lanes and can be more generous.