so do I actually have a full 8 data lane to PCIe slot G3x16 length, x8 pins, *x4? data lanes m.2 hyper card mode gets 2x2... now post BETA-bios 3thousand something my boot raid 0 failed (not a sentimental loss down for the raid0 shenanigans) I'm showing x4+x4// x4 on both drives via RST software, which accurately showed when running (even in failed state) at x2 in a different x4 (via AiC) slot due to lane overuse?,***could we get a detailed block diagram for under $5,000 or is that a thing of the past. Its (*speculation, obvi*)common knowledge to those who care to look at them that poorly consumer platforms are a this OR that allotment,, would be decent of you to share with us when and how known PCIe: allocation, reduction, sharing, splitting, etc.,, is going to or may happen I learn more from partner manufacturing guides from intel than your product recourses ,,***** however the current situation deriving from server class core counts in consumer sockets, *uninformed speculation again obi* if you tell your cores to use different voltages do they? not mine,,, much of said resources are less apt to present themselves,,, google raptor lake die shots and find dead end image links a plenty,,,,, if I'm able to rebuild my array via that slot gen 3 x*2x2/?4x4?/-8***haven't plugged other AiC's in yet. Not sure if that's a possibility yet also could just be a bios inquisitive not hopeful, I'm not particularly kind to this platform, last bios once offered me gen 5 speed on the second x2 via that 🤗 /gen3x16 slot. Notes section thing can just be deleted if STABILITY stabilization +/- some or none is all its going to say, Free PCIe lanes has a better ring to it. i would click that on a company's site with a GDP like yours...,,,While your giving away intel hardware unlocks, consider posting a VROC enabled bios!!! 😂kind of not kidding 🙄 cough email cough... FYP
Poor Boi Strix -Z690 D4
