10-04-2022 06:30 AM - last edited 3 weeks ago by Silent_Scone
ill use this thread to collect some new test bioses for the boards, maybe also to explain some less understood options
to disable cores ccd go here and choose ccd xx bit map down core.
each ones stand for an enabled core
best to disable from the back, ie:
110000
instead of 0011000
after selection press downcore apply changes or discard if made mistake
ocpak/octools
FAQ:
7950x not boosting pass 5.5G -> check that CStates is not disabled
Detailed Explanation on CState Boot Limiter
Test BIOSes:
new:
X3D OC Preset for those MB with asynch BCLK Support: (for simple slight perf boost for X3D)
DOCP/EXPO Tweaked: (for simple timings tightening)
strixe-e 1515
for crosshair and strix e-e:
explanation of segment2 Loadline:
customize a heterogenous loadline for a dual segment workload range.
example above shows loadline=L6 when current is in range of 0~40A, and Level4 when current is above 40A.
Adds for x3d
dynamic ccd priority switch with core flex, os / driver agnostic so win10 win11 ok
Algo as follows:
If condition reached and ccd0 specified, then check current mem/cache activity > threshold and hysteresis reached, if fulfilled then switch
If condition reached and ccd1 specified, then check current mem/cache activity <=threshold and hysteresis reached,, if fulfilled then switch
Default hysteresis =4
Can combine multiple algos for ccd priority so combinations are wide
works on non x3d too but of course senseless on it. detailed explanation here.
11-06-2024 10:17 AM
@Silent_Scone wrote:How are you testing the memory stability prior to trying to enable it?
LOL !
There is no stability at all, after update to 2506, when enabling MCR: the PC will crash within one minute after each reboot, even in the BIOS setting pages (making it a challenge to revert to MCR off).
I have been using the exact same settings for over a year now, with all release BIOSes and most beta BIOSes from 1101 to 3506, and I never have had any stability issue (and I am a programmer with 45+ years of experience, using this PC for heavy compilation tasks daily).
After this dreaded update to 2506, I cannot any more get MPD enabled: it shows "Enabled" when I set it in ASUS and/or AMD settings (I tried all combination of Enabled and Auto: see my posts above), but when I save the settings, the list of changes still shows it as disabled, and after reboot/re-train, when I manage to boot under Windows without crashing and fire ZenTimings, the latter does show PowerDown: Disabled.
What I do not get is why I cannot even get it to work any more with BIOS 2403 and 2505 (while they did work fine before) after 2506 crippled my system, but have it working fine with 2204.
It should be easy for ASUS' engineers to find out though, since it is obviously something that got changed in the three days (if to believe the BIOS date stamp) that elapsed between 2505 and 2506 building.
11-06-2024 10:23 AM
MCR bypasses training routines, there's not much point enabling it if the memory overclock isn't stable, hence my asking.
Not sure how 45 years of programming experience is relevant to memory training, but you might want to list the memory kit PN at least. If the memory is unstable when rolling back, then the OC was probably conditional to begin with.
11-06-2024 10:47 AM - edited 11-06-2024 10:49 AM
@Silent_Scone wrote:MCR bypasses training routines, there's not much point enabling it if the memory overclock isn't stable, hence my asking.
Not sure how 45 years of programming experience is relevant to memory training, but you might want to list the memory kit PN at least. If the memory is unstable when rolling back, then the OC was probably conditional to begin with.
This kit is 100% stable. It is in the QVL list and supported by ASUS "Expo tweaked", which I am using (since it gives me lower latency), without any other change (no overclocking whatsoever, no fiddling with the timings beyond those provided by ASUS in its "tweaked" settings).
I gave the memory kit model already (see above, and also see the ZenTimings screen shot): KF560C36BBEK2-64
The memory is stable when I roll back and PowerDown actually gets enabled together with MCR: these must be kept in sync, or you get crashes: this is NOT an issue with memory timing or frequency. This is a well known AMD IMC bug that AMD never fixed despite some claims.
The problem is that, after flashing 2506, MPD cannot be enabled any more, even after rolling back (be it via EZ Flash or Flash Back: I tried both, see my first post above) to 2403 or 2505: the latter will show MPD "Enabled" in the BIOS settings, but it is a lie (confirmed via ZenTimings).
I can get MPD enabled only after a roll back to 2204, but if I try again to update to 2403 or 2505, I run again in the same problem where MPD is always disabled !
11-06-2024 11:22 AM
QVL is guidance, not assurance - and EXPO is very much overclocking. If the system is stable at stock but not when overclocked, it has everything to do with timings and frequency. You need to ensure a level of stability before enabling settings which circumvent or retain training parameters such as MCR. New firmware and microcode can sometimes "break" overclocking.
Enable EXPO and check memory stability with Karhu Ramtest.
11-06-2024 12:10 PM
@Silent_Scone wrote:QVL is guidance, not assurance - and EXPO is very much overclocking. If the system is stable at stock but not when overclocked, it has everything to do with timings and frequency. You need to ensure a level of stability before enabling settings which circumvent or retain training parameters such as MCR. New firmware and microcode can sometimes "break" overclocking.
Enable EXPO and check memory stability with Karhu Ramtest.
Again, the memory is perfectly stable and has been so for over a years at these settings. This has been tested with several nights long sessions with Memetest86+, and I never had a single crash in all those months, with MCR+MPD enabled !!!
This PC is used 18H/24 everyday: had there been any memory instability, I would have crashed !
The crash caused by BIOS 2506 is happening only because MPD is not being properly enabled in the BIOS, NOT by memory timings.
11-06-2024 01:59 PM - edited 11-06-2024 02:00 PM
You don't need MPD or MCR enabled, it's not compulsory. If the system isn't stable without these enabled, then the OC is unstable.
Memtest86 isn't sufficient, use Karhu or TM5, HCI Memtest Pro, etc. The fact you're claiming MPD isn't being enabled is secondary at the moment. I don't see anyone else reporting this
11-06-2024 03:12 PM
You are 100% wrong, I'm afraid... This is indeed a BIOS bug, and I found why it happens and how to work around it.
See my post on next page, dated "2024-11-06 11:02 PM"
11-10-2024 05:31 AM - edited 11-10-2024 05:51 AM
I'm having the same "problem" regarding MPD. Tried with all 3 occurrences set to Enabled, as well as only the first one [Enabled] and the rest [Auto]. In all cases ZenTimings reports MPD Disabled.
X670E-E on 2506. NO idea if this was happening on previous versions or not. Maybe @dinosaur should try MC Voltage 1.40 or 1.41V as that makes it stable for me even if MPD is Disabled (as it seems). I didn't even know about this until now. That may explain why I needed to increase voltages in order to avoid 0d reboot issues.
Later edit: Tried what @dinosaur suggested (even with SoC/uncore), MPD is still Disabled. Not that I care much about it as long as it's stable...
11-10-2024 06:33 AM
Set Memory Context Restore to Enabled and Power Down should automatically enable as has been the case for sometime. If not, you can report back.
Tuning the voltage rails so the system is stable enough to pass POST stress tests is the right process, regardless of whether you then wish to circumvent them under certain conditions thereafter by enabling MCR
11-10-2024 07:07 AM
MCR is already enabled, that's not the point. MPD is showing as Enabled in BIOS but Disabled in ZenTimings