10-04-2022 06:30 AM - last edited on 12-02-2024 10:18 PM by Silent_Scone
ill use this thread to collect some new test bioses for the boards, maybe also to explain some less understood options
to disable cores ccd go here and choose ccd xx bit map down core.
each ones stand for an enabled core
best to disable from the back, ie:
110000
instead of 0011000
after selection press downcore apply changes or discard if made mistake
ocpak/octools
FAQ:
7950x not boosting pass 5.5G -> check that CStates is not disabled
Detailed Explanation on CState Boot Limiter
Test BIOSes:
new:
X3D OC Preset for those MB with asynch BCLK Support: (for simple slight perf boost for X3D)
DOCP/EXPO Tweaked: (for simple timings tightening)
strixe-e 1515
for crosshair and strix e-e:
explanation of segment2 Loadline:
customize a heterogenous loadline for a dual segment workload range.
example above shows loadline=L6 when current is in range of 0~40A, and Level4 when current is above 40A.
Adds for x3d
dynamic ccd priority switch with core flex, os / driver agnostic so win10 win11 ok
Algo as follows:
If condition reached and ccd0 specified, then check current mem/cache activity > threshold and hysteresis reached, if fulfilled then switch
If condition reached and ccd1 specified, then check current mem/cache activity <=threshold and hysteresis reached,, if fulfilled then switch
Default hysteresis =4
Can combine multiple algos for ccd priority so combinations are wide
works on non x3d too but of course senseless on it. detailed explanation here.
Solved! Go to Solution.
02-05-2025 04:14 AM
I think it would be wise to use one or the other. I was always under the impression that you should either use the AMD overclocking menu or the main one.
As far as which on would be better, I have no idea. I always use the PBO settings on the main menus. But try it out. Couldn't hurt!
02-05-2025 05:16 AM - edited 02-05-2025 05:21 AM
Thanks. As of this moment I'm using Both. The reason Im also using the Advanced AMD PBO is it allows you to default PBO limits to the Motherboards parameters. Otherwise I wouldnt fool with the advanced amd page.
I'm Currently Running PBO+200+Asynchronous eCLK 104.5
Curve Shaper has room for improvement, but I'm currently having to use Positive +10 on High and Maxiumum frequencies and a -17 on the Min, Low, and Medium frequencies. I tried +5 and it caused Cinebench to freeze up. Maybe I should just back the eCLK down to 104 instead of 104.5. I'm getting pretty decent Cinebench R23 scores on multi core test of about 24,460 Pts. CPU-Z Multi of 9360 and single 896.
Should I stick to EXPO 1 or use EXPO Tweaked on my Gskill 2x16GB DDR5 6000 CL28-36-36-96 @ 1.40v stock RAM kit. I know EXPO Tweaked's tighter sub timings might lead to memory errors. I really hate doing a bunch of memory stability tests for minimal gains. I may just go back to EXPO I and call it a day. My ram is air cooled with dual 60mm fans on top of the DIMMs. tREFI set to 65,535.
02-05-2025 11:17 AM
Patiently waiting for TUF GAMING X670E-PLUS WIFI to get a stable bios update - how are people doing on 3203?
02-05-2025 11:50 AM
Not a single issue here on any of the last beta versions.
02-05-2025 02:20 PM - edited 02-05-2025 02:21 PM
any idea if we may be getting a new beta BIOS for the Asus ROG Crosshair x870E Hero anytime soon? I don't have any issues with 1003. I was just curious if a 1004 was being worked on at the moment?
Thank you
02-06-2025 06:47 AM - edited 02-06-2025 06:58 AM
I apologize for the multiple posts back to back, but can someone please tell me what the equivalent to intel's 13/14th gen z790 memory controller voltage is on amd AM5/x870e platform? I understand CPU SoC voltage is like the System Agent voltage on Intel. I'm trying to figure out how to increase the voltage of the correct memory controller to improve DDR5 memory stability for reducing my timings on my G.Skill 2x16GB(32GB) DDR5 6000 CL28-36-36-96 @ 1.40v kit. I have manually set cpu SoC voltage to a manual 1.25v and I tried increasing VDD/VDDQ ram voltage from the stock 1.40v to 1.45v just to run CL26-36-36-96 along with some tighter sub-timings. I got an error in karhu fairly quickly. So I imagine increasing the memory controller voltage would improve stability in my case rather than just adding more VDD/VDDQ voltage? Also, what is a good voltage range to work with on the 9800x3D's memory controller? On my 13900KS I would use anywhere between 1.45-1.50v memory controller to run DDR8000 2x24GB sticks stable depending on how aggressive my timings were or if I wanted to push it to 8200.
Thanks for any help!
02-06-2025 10:11 PM - edited 02-06-2025 10:14 PM
In AM5 (Zen 4/5) VSoC also controls voltage of Integrated Memory Controller (IMC), so VSoC is crucial for RAM stability.
Higher frequency when using 1:1 mode requires higher VSoC, so basically pushing UCLK higher means higher VSoC, VSoC is not a big issue when using 2:1 mode because of the ratio not pushing UCLK.
Using dual rank RAM / using all the 4 slots is also a burden the IMC, makes overclocking, even enabling EXPO much harder.
When using 1:1 mode, Zen 4/5 usally tops out at 6400MT/s (6600 if you got a really good / golden sample).
VSoC and FCLK stability has a inverse ratio, higher FCLK likes lower VSoC.
Also keeping the VSoC at lowest stable point is the best, lowering VSoC gives more headroom to core power.
Adjusting subtimings and such should not change stability of VSoC, increase / play with memory VDD, VDDQ, VDDP and VPP (mainly VDD, other voltages might require tuning when trying higher frequencies).
So if you are running 6000, i would lower VSoC to the lowest stable point, you probably could go down around 1.1V, might require some trial and error.
I've posted a link Buildzoid's timings also added some changes in previous page, you can try that.
02-07-2025 12:50 AM
I really appreciate your help kind sir! I just wanted to tighten sub timings up more along with going from stock 28 to 26CL and stay at 6000. i set my vSoC from auto of 1.243v to 1.25v manually. but I might just put it back on auto? Buildzoid quick timings recommends 1.25v vSoc for tightened sub timings on ddr 6000.
02-07-2025 12:59 AM
Buildzoid recommends 1.25v because the possibility of getting extremely bad luck on IMC.
You can try to drop VSoC even further, 1.15V should be fine at 6000 on most chips, still, like i've said before it might require some trail and error.
02-07-2025 02:10 AM - edited 02-07-2025 02:10 AM
Up to 1.3v is fine, no reason not to trust the auto-rules at this late stage. Obviously, manual tuning is welcome that's why all these rails are openly adjustable - it's just that some CPUs need the voltage.