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X670 resource


ill use this thread to collect some new test bioses for the boards, maybe also to explain some less understood options

to disable cores ccd go here and choose ccd xx bit map down core.
each ones stand for an enabled core
best to disable from the back, ie:
instead of 0011000
after selection press downcore apply changes or discard if made mistake

octool port to linux

7950x not boosting pass 5.5G -> check that CStates is not disabled
Detailed Explanation on CState Boot Limiter

Test BIOSes:

X3D OC Preset for those MB with asynch BCLK Support: (for simple slight perf boost for X3D)

DOCP/EXPO Tweaked: (for simple timings tightening)

strixe-e 1515 

strixe-f 1515 

strix e a 1515 

crosshair hero 1515 

crosshair gene 1515 

crosshair extreme 1515 

creator 670 1515

creator b650 1515

strix 650E I

strix 670 itx



for crosshair and strix e-e:

explanation of segment2 Loadline:


customize a heterogenous loadline for a dual segment workload range.

example above shows loadline=L6 when current is in range of 0~40A, and Level4 when current is above 40A.




Adds for x3d

dynamic ccd priority switch with core flex, os / driver agnostic so win10 win11 ok



Algo as follows:
If condition reached and ccd0 specified, then check current mem/cache activity > threshold and hysteresis reached, if fulfilled then switch
If condition reached and ccd1 specified, then check current mem/cache activity <=threshold and hysteresis reached,, if fulfilled then switch
Default hysteresis =4

Can combine multiple algos for ccd priority so combinations are wide

works on non x3d too but of course senseless on it. detailed explanation here.

1,556 REPLIES 1,556

Don't bother with that guy, he acts like he's pro but he keeps on telling nonsenses.

BTW forget about global CO, it's plain crap, do your proper per core CO.
For example my brother's CO goes from +10 to -10 with 103 bclk and 0 to -25 with 100 bclk.
My stable per core for 1303 is: 29 22 22 28 25 32 25 36 20 12 23 18 18 14 29 21 (no async bclk on my e-a)
If we used global CO my brother would be stable at +10 or 0 and mine would be at 12, huge loss !

Our protocol (not meant to be universal or mandatory for everyone, just our protocol based on our experiences and tests that point cores on error):
- core cycler's ycruncher 13-HSW ~ Airi all test random 1.5m no suspend
- then core cycler's ycruncher 22-ZN4 ~ Kizuna all test random 1.5m no suspend
- then OCCT small extreme variable auto sse
- then OCCT large extreme variable auto avx2
- then OCCT large extreme variable auto avx512
In this order until each step throws no error, daily and overnight for core cycler and overnight only for OCCT.

Since then we had no games, video encoding or music encoding crash, no bsod at all even at idle.

Thanks I'll check those tools, OCCT seems particularly interesting ^^

I had started to do per core settings, but it was too long and tedious for me. Maybe I'll do a second pass, I should have some free time next week.

Level 10

At least MCR and PowerDown enabled works okay for “me” with EXPO off/on (1303). Cold to Windows sign in in average of 20-31s. 

2x32G G.Skill Trident Z5 Neo CL30 (QVL)

With Expo off, PBO on, MCR on, PowerDown on

4800MT/s > 20-21s till windows sign in

With Expo on, PBO on, MCR on, PowerDown on

6000MT/s > 23-31s till windows sign in


sticking to 1303 - no compromise here for me 🙂

Level 9

well, the legal disclamers are gone from bios downloads...

What does it mean then? Full support nonetheless? 

Level 9

Does 1303 bios fix soc voltages or we need to wait for proper bios fix?


It doesn't but no problem if you manually fix vsoc at 1.25V.

However vsoc fixed stable bios and hopefully correct OCP will be after 1412 which is test bios so no support.

Level 10

im getting high vcore (1.4v) for longer periods during cb23. is this normal/healty?

7950x3d / bios 1410

pbo autolimits and co -15

Let me guess… 1.396? That’s at least what I see in HWMonitor 🙂

it maxed out at 1.41 during corecycler