ill use this thread to collect some new test bioses for the boards, maybe also to explain some less understood options
to disable cores ccd go here and choose ccd xx bit map down core.
each ones stand for an enabled core
best to disable from the back, ie:
110000
instead of 0011000
after selection press downcore apply changes or discard if made mistake
ocpak/octools
octool port to linux
FAQ:
7950x not boosting pass 5.5G -> check that CStates is not disabled
Detailed Explanation on CState Boot Limiter
Test BIOSes:
new:
X3D OC Preset for those MB with asynch BCLK Support: (for simple slight perf boost for X3D)
DOCP/EXPO Tweaked: (for simple timings tightening)
strixe-e 1515
for crosshair and strix e-e:
explanation of segment2 Loadline:
customize a heterogenous loadline for a dual segment workload range.
example above shows loadline=L6 when current is in range of 0~40A, and Level4 when current is above 40A.
Adds for x3d
dynamic ccd priority switch with core flex, os / driver agnostic so win10 win11 ok
Algo as follows:
If condition reached and ccd0 specified, then check current mem/cache activity > threshold and hysteresis reached, if fulfilled then switch
If condition reached and ccd1 specified, then check current mem/cache activity <=threshold and hysteresis reached,, if fulfilled then switch
Default hysteresis =4
Can combine multiple algos for ccd priority so combinations are wide
works on non x3d too but of course senseless on it. detailed explanation here.
Squidbean wrote:
If I enable Medium Load Bootlit, I can only run an all core of negative 5, even 10 eventually crashes it seems. single core scores around 2019 in cb23 (vs 2005 with my other all negative 20 setup). The multicore score suffers, gets just above 38k, where my other setup gets around 38.63k multi core score.
It's hard to know eaxctly how this affects real world use cases, as with negative -20 all core, I still boost to 5750 it seems, but using medium load bootlit, it def boosts higher, 5870 ish but I'm not sure its worth the hit to all core not having as good all core offset.
Interesting to compare for sure.
All-Core CO is generally not advised, especially as you go up in core count. It is generally best to adjust CO core by core because there can be significant variation in quality between individual cores. It's also important to note that each individual core has a different voltage vs. frequency curve based on its quality. A CO value of -5 on your "best" core may boost higher than a CO of -10 on one of the lower quality cores (you can use HWInfo to identify them as shown in Fig.1 below and the OCPack linked in the OP has a tool for showing you the actual V/F curves for each core). This means that while an "all-core" CO looks "flat," it isn't and will actually push your better cores much harder than the rest.
Following from that, when you leave AMD's C-State limiter in place, you drastically decrease the likelihood of the CPU boosting past 5.5GHz and finding its limits. This is because, in practice, even with relatively clean OS installs, there is still a lot going on in the background, making scenarios with fewer than 4 cores active extremely rare. When I disable boost it, I almost never see any core go over 5.5GHz unless I start in safe mode or manually shut down tons of applications and services. I may see HWInfo register a momentary spike to something higher, but never more than a split second and lower than with Medium Load BoostIt enabled.
With the Per-Core Boost Limit in the BIOS, you can manually cap the individual cores to prevent them going over stable limits. So far, I have all of CCD 1 at 5600 except for cores 1 and 4, which are both limited to 5750. To go over 5750 on those cores, I have to bump the CO for them from -10 to 0. With a Per-Core CO and Boost Limits but BoostIt enabled, I can get a single core of 2072 and multi core of 39461, but I have to go from CO 0 on core 4 for the single core to boost over 5750 for that test, to CO -10 on core 4 for the multi-core to stay just a little cooler.
I think this is where I need to start playing with the dynamic OC switcher to go from a CO based low-thread setup to a static manual OC for heavy multi-core loads, but I don't have the time for it right now.
Fig. 1:
Edit to fix links and to add that if you push your CO values too low, you can experience clock stretching, as a core will try to maintain stability by slowing down. If you see a significant gap (more than say, 50MHz) between "Core Clock" values and "Effective Clock" values when under an efficient load like Cinebench, that is an indication that you are experiencing clock stretching. It's normal for the clock and effective clock to differ vastly at idle as the clock is waiting for work to do, but when a heavy workload is active, the clocks should be very close.
@Shamino,..
Thanks for 0921 update with AGESA 1005c_RC3. :cool:
Thanks for 0921 update with AGESA 1005c_RC3. :cool:
