10-04-2022 06:30 AM - edited 10-18-2023 07:20 AM
ill use this thread to collect some new test bioses for the boards, maybe also to explain some less understood options
to disable cores ccd go here and choose ccd xx bit map down core.
each ones stand for an enabled core
best to disable from the back, ie:
110000
instead of 0011000
after selection press downcore apply changes or discard if made mistake
ocpak/octools
FAQ:
7950x not boosting pass 5.5G -> check that CStates is not disabled
Detailed Explanation on CState Boot Limiter
Test BIOSes:
new:
X3D OC Preset for those MB with asynch BCLK Support: (for simple slight perf boost for X3D)
DOCP/EXPO Tweaked: (for simple timings tightening)
strixe-e 1515
for crosshair and strix e-e:
explanation of segment2 Loadline:
customize a heterogenous loadline for a dual segment workload range.
example above shows loadline=L6 when current is in range of 0~40A, and Level4 when current is above 40A.
Adds for x3d
dynamic ccd priority switch with core flex, os / driver agnostic so win10 win11 ok
Algo as follows:
If condition reached and ccd0 specified, then check current mem/cache activity > threshold and hysteresis reached, if fulfilled then switch
If condition reached and ccd1 specified, then check current mem/cache activity <=threshold and hysteresis reached,, if fulfilled then switch
Default hysteresis =4
Can combine multiple algos for ccd priority so combinations are wide
works on non x3d too but of course senseless on it. detailed explanation here.
Solved! Go to Solution.
10-19-2022 05:25 AM
Tsikos wrote:
Yesterday i build my new rig with asus rog x670e-e strix board and i have problem with network, for some reason the ethernet auto disable the internet and must reboot the system to get internet again but this happened every 10-20 minutes after boot any solutions?
10-19-2022 05:31 AM
Tyberious wrote:
I had this same issue. Go to device manager and open the 10G NIC click advanced tab and disable both Recv Segment Coalescing ipv4 and ipv6.
10-19-2022 05:37 AM
Tsikos wrote:
I have the Intel Ethernet Controller I225-V controller and cant see this option in advanced tab, maybe have a different name?
10-19-2022 05:41 AM
Tyberious wrote:
Ah, sorry I thought you had the Marvell 10g. Sorry, I am sure it's a similar issue, but I don't know the options on the intel chips. Someone from Asus will need to help with that one since my quick research says it's a top reported issue with that chip.
10-20-2022 04:28 AM
10-20-2022 04:54 AM
Nico67 wrote:
I have been trying to get per core boost limiter work with an Async103.6+mlb tune, however I can't get it to limit anything like I have set it. usually it doesn't limit at all, or it ends up dropping from 55.5x down to 55x giving me 5698, or lastly 4599 which doesn't seem to tie up with anything. I have tried setting it to straight frequency like 5675 or 5675/1.036, but it doesn't seem to limit a core as I would have expected. I started with 0801 bios but tried 0041 and it gives the same result.
I am wondering if it doesn't work with external clk enabled, may try that next just to see it work.
10-20-2022 10:20 PM
Shamino wrote:
i presume u are not oc mode (not setting ratios manually) if u override ratios it wont work
it doesnt take into account bclk, did you do the appropriate adjustments?
u pin the workload to a specific core?
10-20-2022 10:57 PM
Nico67 wrote:
Async 103.6 + mlb and 5439 DOS
Max should be 5749 ish and I tried setting things like 5675 or 5478 (less the blk) and run CB23 single with affinity locked to a core.
Hows does it implement the limit? does it fix to the nearest .25 ratio like 54.75?
10-22-2022 08:42 PM
Shamino wrote:
yes now i see the same thing
when the bclks are different in asynch mode, when they are different then i couldnt find a freq iinput that wouldnt over shoot or undershoot alot.
i will have to check if it is possible to co exist per core limit with asynch bclk.
10-26-2022 04:33 AM
Shamino wrote:
yes now i see the same thing
when the bclks are different in asynch mode, when they are different then i couldnt find a freq iinput that wouldnt over shoot or undershoot alot.
i will have to check if it is possible to co exist per core limit with asynch bclk.