strix x670e-f pcie lanes gpu only running pcie 5 x 8

[Fletcherea]

I cannot get my 5080 Prime (non oc) running at 5 x16 for the life of me, 9800x3d, and two nvme drives, down to one drive, and have tried it in all slots, still only 5x8 speed for the gpu.  Strix x670e-f uefi has it set to gen 5 (tried auto as well) and pcie is set to 16.  At a loss here, cannot figure this one out, on the 2704 BIOS, gpu is in the top slot obviously, thanks in advance folks

[Silent_Scone]

Hi @Fletcherea 

If the GPU is refusing to run at full width when the NVME drive is present in M.2_3 and M.2_4: 

Ensure the GPU is fully seated.

If using a riser cable, remove and connect the GPU directly to the PCIEX16_1 port.

Reseat the CPU. Inspect the socket and CPU pin pad for any debris or damage - remount ensuring consistent mounting pressure.

If using a third-party CPU contact frame, remove and use the stock retention mechanism.

[gupsterg]

@Fletcherea 

Very strange you have this issue. I checked the AM5 googlesheet and manual/techspecs on ASUS site twice, that board doesn't do lane sharing so should be full 16x PCI-E.

Besides the suggestions by Silent Scone, perhaps try latest beta UEFI for your board, 2804.

What application are you using to see PCI-E lanes configuration? as in the past I have see some apps mis-report it. Also power saving functions can drop PCI-E lanes IIRC, so load GPU up and see what is reported.

[Fletcherea]

Popped out the 9800x3d, and sure enough I noticed a small row of bent pins, what a friggin bummer!  That's got to be the culprit.   I rebuilt my old amd 5600x system, popped in the 5080, and sure enough it was running 4 x 16.  The dang cpu pins never even crossed my mind, thanks guys.  Past return period, so it's the grueling rma process time ><  And of course I'll get blamed for the pins 

[Silent_Scone]

Hi @Fletcherea 

Sorry to hear that. Often it will be related to the socket or substrate if there's no obvious reason.

[gupsterg]

Thank you for update. Sorry to read bent pins, I hope RMA goes well.