ASUS ROG Strix B650E-F Gaming WiFI: GPU running in only PCI-E Gen4 x8 instead of x16

[JRepin]

I have just bought a new GPU (Powercolor Hellhound AMD Radeon RX 7900 GRE) which supports PCI-E x16 as does the motherboard (using BIOS v2616). But when I use various tools they show the GPU is runing in 8x only instead of x16. I have tried to debug this and first checked the BIOS and I could not find any setting to force it ot x16 or any diagnostic util in BIOS to show the PCI-E configuration the GPU is running with. The only thing I found is the PCIEX16_1 Bifurcation setting/option, which is set to Auto and can not be set to Disabled/x16. All other options there are with x8 or x4.

I have also checked the Linux kernel messages in dmesg and could see that it reports things like:
[    0.225889] [      T1] pci 0000:01:00.0: 126.024 Gb/s available PCIe bandwidth, limited by 16.0 GT/s PCIe x8 link at 0000:00:01.1 (capable of 252.048 Gb/s with 16.0 GT/s PCIe x16 link)
[    0.226526] [      T1] pci 0000:03:00.0: 126.024 Gb/s available PCIe bandwidth, limited by 16.0 GT/s PCIe x8 link at 0000:00:01.1 (capable of 252.048 Gb/s with 16.0 GT/s PCIe x16 link)

The output of lspci command also confirms the reduced lanes usage (note the LnkCap and LnkSta info):

00:01.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14db (prog-if 00 [Normal decode]) 
       Subsystem: ASUSTeK Computer Inc. Device 8877 
       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
       Latency: 0, Cache Line Size: 64 bytes 
       Interrupt: pin ? routed to IRQ 27 
       IOMMU group: 1 
       Bus: primary=00, secondary=01, subordinate=03, sec-latency=0 
       I/O behind bridge: f000-ffff [size=4K] [16-bit] 
       Memory behind bridge: f6b00000-f6dfffff [size=3M] [32-bit] 
       Prefetchable memory behind bridge: f800000000-fc0fffffff [size=16640M] [32-bit] 
       Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
       BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B- 
               PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
       Capabilities: [50] Power Management version 3 
               Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
               Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
       Capabilities: [58] Express (v2) Root Port (Slot+), IntMsgNum 0 
               DevCap: MaxPayload 512 bytes, PhantFunc 0 
                       ExtTag+ RBE+ TEE-IO- 
               DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- 
                       RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ 
                       MaxPayload 256 bytes, MaxReadReq 512 bytes 
               DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- 
               LnkCap: Port #0, Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <64us 
                       ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ 
               LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ 
                       ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
               LnkSta: Speed 16GT/s, Width x8 
                       TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ 
               SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- 
                       Slot #0, PowerLimit 75W; Interlock- NoCompl+ 
               SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- 
                       Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- 
               SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- 
                       Changed: MRL- PresDet- LinkState+ 
               RootCap: CRSVisible+ 
               RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible+ 
               RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
               DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+ 
                        10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1 
                        EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- 
                        FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd+ 
                        AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS- 
               DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- 
                        AtomicOpsCtl: ReqEn- EgressBlck- 
                        IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq- 
                        10BitTagReq+ OBFF Disabled, EETLPPrefixBlk- 
               LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS- 
               LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis- 
                        Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
                        Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot 
               LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+ 
                        EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest- 
                        Retimer- 2Retimers- CrosslinkRes: unsupported 
       Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ 
               Address: 00000000fee00000  Data: 0000 
       Capabilities: [c0] Subsystem: ASUSTeK Computer Inc. Device 8877 
       Capabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+ 
       Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> 
       Capabilities: [270 v1] Secondary PCI Express 
               LnkCtl3: LnkEquIntrruptEn- PerformEqu- 
               LaneErrStat: LaneErr at lane: 1 2 3 4 5 6 7 
       Capabilities: [2a0 v1] Access Control Services 
               ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ 
               ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- 
       Capabilities: [370 v1] L1 PM Substates 
               L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1- L1_PM_Substates+ 
               L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- 
               L1SubCtl2: 
       Capabilities: [3c4 v1] Designated Vendor-Specific: Vendor=1022 ID=0001 Rev=1 Len=44 <?> 
       Capabilities: [400 v1] Data Link Feature <?> 
       Capabilities: [410 v1] Physical Layer 16.0 GT/s <?> 
       Capabilities: [440 v1] Lane Margining at the Receiver 
               PortCap: Uses Driver- 
               PortSta: MargReady- MargSoftReady- 
       Capabilities: [500 v1] Physical Layer 32.0 GT/s <?> 

01:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Upstream Port of PCI Express Switch (rev 10) (prog-if 00 [Normal decode]) 
       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
       Latency: 0, Cache Line Size: 64 bytes 
       Interrupt: pin A routed to IRQ 32 
       IOMMU group: 12 
       Region 0: Memory at f6d00000 (32-bit, non-prefetchable) [size=16K] 
       Bus: primary=01, secondary=02, subordinate=03, sec-latency=0 
       I/O behind bridge: f000-ffff [size=4K] [16-bit] 
       Memory behind bridge: f6b00000-f6cfffff [size=2M] [32-bit] 
       Prefetchable memory behind bridge: f800000000-fc0fffffff [size=16640M] [32-bit] 
       Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
       BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B- 
               PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
       Capabilities: [48] Vendor Specific Information: Len=08 <?> 
       Capabilities: [50] Power Management version 3 
               Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
               Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
       Capabilities: [58] Express (v2) Upstream Port, IntMsgNum 0 
               DevCap: MaxPayload 512 bytes, PhantFunc 0 
                       ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 75W TEE-IO- 
               DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ 
                       RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ 
                       MaxPayload 256 bytes, MaxReadReq 512 bytes 
               DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend- 
               LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <64us 
                       ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ 
               LnkCtl: ASPM L1 Enabled; LnkDisable- CommClk+ 
                       ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
               LnkSta: Speed 16GT/s, Width x8 (downgraded) 
                       TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
               DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+ 
                        10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 4 
                        EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- 
                        FRS- 
                        AtomicOpsCap: Routing+ 32bit- 64bit- 128bitCAS- 
               DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- 
                        AtomicOpsCtl: EgressBlck- 
                        IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq- 
                        10BitTagReq+ OBFF Disabled, EETLPPrefixBlk- 
               LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS- 
               LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis- 
                        Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
                        Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot 
               LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+ 
                        EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest- 
                        Retimer- 2Retimers- CrosslinkRes: unsupported 
       Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
               Address: 0000000000000000  Data: 0000 
       Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> 
       Capabilities: [150 v2] Advanced Error Reporting 
               UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- 
                       ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- 
                       PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- 
               UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- 
                       ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- 
                       PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- 
               UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ 
                       ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr- 
                       PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- 
               CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr- HeaderOF- 
               CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr- HeaderOF- 
               AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- 
                       MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- 
               HeaderLog: 00000000 00000000 00000000 00000000 
       Capabilities: [270 v1] Secondary PCI Express 
               LnkCtl3: LnkEquIntrruptEn- PerformEqu- 
               LaneErrStat: LaneErr at lane: 1 2 3 4 5 6 7 
       Capabilities: [320 v1] Latency Tolerance Reporting 
               Max snoop latency: 0ns 
               Max no snoop latency: 0ns 
       Capabilities: [400 v1] Data Link Feature <?> 
       Capabilities: [410 v1] Physical Layer 16.0 GT/s <?> 
       Capabilities: [440 v1] Lane Margining at the Receiver 
               PortCap: Uses Driver- 
               PortSta: MargReady+ MargSoftReady- 

03:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 31 [Radeon RX 7900 XT/7900 XTX/7900M] (rev ce) (prog-if 00 [VGA controller]) 
       Subsystem: Tul Corporation / PowerColor Device 2425 
       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 
       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
       Latency: 0, Cache Line Size: 64 bytes 
       Interrupt: pin A routed to IRQ 40 
       IOMMU group: 14 
       Region 0: Memory at f800000000 (64-bit, prefetchable) [size=16G] 
       Region 2: Memory at fc00000000 (64-bit, prefetchable) [size=256M] 
       Region 4: I/O ports at f000 [size=256] 
       Region 5: Memory at f6b00000 (32-bit, non-prefetchable) [size=1M] 
       Expansion ROM at f6c00000 [disabled] [size=128K] 
       Capabilities: [48] Vendor Specific Information: Len=08 <?> 
       Capabilities: [50] Power Management version 3 
               Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+) 
               Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
       Capabilities: [64] Express (v2) Legacy Endpoint, IntMsgNum 0 
               DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited 
                       ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- TEE-IO- 
               DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ 
                       RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ 
                       MaxPayload 256 bytes, MaxReadReq 512 bytes 
               DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend- 
               LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <1us 
                       ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ 
               LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ 
                       ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
               LnkSta: Speed 16GT/s, Width x16 
                       TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
               DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+ 
                        10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1 
                        EmergencyPowerReduction Form Factor Dev Specific, EmergencyPowerReductionInit- 
                        FRS- 
                        AtomicOpsCap: 32bit+ 64bit+ 128bitCAS- 
               DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- 
                        AtomicOpsCtl: ReqEn+ 
                        IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq- 
                        10BitTagReq+ OBFF Disabled, EETLPPrefixBlk- 
               LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS- 
               LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis- 
                        Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
                        Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot 
               LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+ 
                        EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest- 
                        Retimer- 2Retimers- CrosslinkRes: unsupported 
       Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ 
               Address: 00000000fee00000  Data: 0000 
       Capabilities: [150 v2] Advanced Error Reporting 
               UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- 
                       ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- 
                       PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- 
               UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- 
                       ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- 
                       PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- 
               UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ 
                       ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr- 
                       PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- 
               CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrIntErr- HeaderOF- 
               CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr- HeaderOF- 
               AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- 
                       MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- 
               HeaderLog: 00000000 00000000 00000000 00000000 
       Capabilities: [200 v1] Physical Resizable BAR 
               BAR 0: current size: 16GB, supported: 256MB 512MB 1GB 2GB 4GB 8GB 16GB 
               BAR 2: current size: 256MB, supported: 2MB 4MB 8MB 16MB 32MB 64MB 128MB 256MB 
       Capabilities: [270 v1] Secondary PCI Express 
               LnkCtl3: LnkEquIntrruptEn- PerformEqu- 
               LaneErrStat: 0 
       Capabilities: [410 v1] Physical Layer 16.0 GT/s <?> 
       Capabilities: [450 v1] Lane Margining at the Receiver 
               PortCap: Uses Driver- 
               PortSta: MargReady+ MargSoftReady- 

I think nothing in the motherboard should be sharing PCI-E resources and causing the reduced number of lanes for the PCIEX16_1 with the GPU. I have these devices in these slots:
PCIEX16_1: the GPU
M.2_2(SOCKET3): the SSD
PCIEX1_2: the Wifi/Bluetooth adapter

What could be causing this problem? Am I missing a setting in the BIOS or something else? IMaybe a bug in the BIOS?

[KedarWolf]

If you have anything in the second PCI-E slot or even the shorter PCI-E slot, your GPU will only run at 8x.

Also, I'm pretty sure if you only have the GPU in the PCI-E slots as the only device being used in them, you need the M.2 on the M.2_1 slot. If you have an M.2 in the M.2_2 slot, the GPU will default to 8x as well.

[JRepin]

Are you sure about this. Because nothing about this is mentioned in the motherboard manual. It only mentions that M.2_3(SOCKET3) is sharing bandwidth with PCIEX16_2 (and does not mention anything about the PCIEX16_1), both connected via CPU thru B650 chipset. There is no mention of PCIEX16_1 sharing anything with M.2 slots, despite M.2_2(SOCKET3) being provided by the Ryzen CPU just like PCIEX16_1. There is also no mention about lanes limitations that I could se in AMD documentation for the CPU. I can only see that it support 24 lanes, which means 16+4+4 and it checks out for PCIEX16_1 + M.2_1 + M.2_2 without sharing. Or have I missed something in the manuals/specs or something?

[KedarWolf]

You need to look at the motherboard manual.

[JRepin]

As I mentioned I did look at the motherboard manual, and according to it there should be no lanes reduction in the configuration I am using. Or I am missing something from the manual (if anyone can point me to the page in manual that explains this would be appreciated), or the manual is not complete, or there is bug in the BIOS, or maybe something else.

[JRepin]

Are any of the ASUS engineers (or some of their support people) even reading this forum? Or should I also report this to their tech support directly?

[davidwilly]

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