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X570 CH8 - Looking for block diagram and if Sata is shared.

xenon2000
Level 7
I have seen plenty of generic AMD block diagrams and read the manual. But I would like a block diagram for the CH8 wifi specifically as boards can deviate from the generic X570 chipset side of the block diagrams.

I am looking to buy this MB to drive a future Zen 3 cpu and just wanted to make sure that the SATA ports are not shared with the X570 chipset M.2_2 port running at PCIE 4.0 x4. Or if SATA is shared... which SATA ports are shared so I can avoid them. According to the specs and manual, none of the 8x SATA ports are shared.
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soilworker4life
Level 7
@xenon2000
Well...
This is a really tough question to answer. If you're concerned about interrupt i/o requests, I have no clue.... if your concern is bandwidth and link speed, well we can suss some things out with the resources available to us.

TL;DR at the bottom 👇

Haven't been able to find a block diagram for the CH8 Hero (WiFi). Dug around the books like you did, plus inferred some things from the CH8 Impact block diagram and the AMD generic Block Diagram.
https://www.anandtech.com/show/14950/the-asus-rog-crosshair-viii-review

https://wccftech.com/asus-x570-motherboards-teased-rog-crosshair-viii-rog-strix-tuf-prime-series/

Notice that in the CH8 Hero (WiFi) manual, the notes section only mentions the M.2_1 link speed considerations based on the generation of CPU the individual uses in the build. That means to me that a hypothetical CH8 Hero (WiFi) block diagram would show direct CPU connection to the M.2_1 socket. I think that's a safe assumption to make, yes? Maybe I have it backwards... but for now, I'm going with it.

If that's true, then the M.2_2 socket would have it's PCIe x4 lanes given to it through the x570 PCH. The PCH has x4 Gen 4 PCIe lanes given to it from the CPU.

Unless you are using all 8 SATA ports AND the M.2_2 socket with a high speed NVMe PCIe Gen4 SSD, It's unlikely that you'd run into PCIe Gen 4 x4 PCH link speed bottlenecks. Using greater than 4 SATA ports might reduce your link speed available for the M.2_2. Say for example you have 4x 2.5" SATA SSDs connected, that'd leave you with roughly 6000 MB/s left over for whatever model NVMe PCIe Gen 4 SSD you had plugged into socket M.2_2. Further still, if you're just using spinning rust on the SATA ports, they can't even come close to saturating even just one x1 dedicated PCIe Gen4 of the 4 lanes given to the x570 chipset. My rough math is based on a single PCIe Gen4 lane equaling 2000MB/s. Hopefully all that is as clear as mud for you? 😅

As an aside, I think the fastest NVMe M.2 these days has theoretical speeds of 7,000MB/s of sequential reads and up to 5,000 MB/s of sequential writes. I think that's the Samsung 980 Pro SSD? Most NVMe M.2 Gen 4 SSDs run at speeds below that.

According to the CH8 Hero (Wifi) manual, all 8 SATA ports go through the x570 chipset, because the PCH handles the RAID 0,1,10 for all 8 SATA ports. If only 6 of the 8 could be RAIDed it would say that in the notes, but that's not the case. So, all 8 SATA ports must go through the x570 PCH in order to implement RAID on them.

TL;DR
Again, IF there are IR SATA conflicts, it would most likely be SATA6G_7 and SATA6G_8 with the M.2_2 socket, but that's a guess. At the theoretical link speeds and modern NVMe Gen 4 speeds, It's doubtful you'd saturate the PCH link with two 2.5" or two 3.5" spinning rust on SATA6G _7 and _8.

What are your thoughts?