The worst memory related issue on this platform is that there is no way to tune the memory controller parameters. They are hard coded into the memory controller firmware (PMU) and cannot be changed by anyone but AMD. This prevents the manufacturers from optimizing the parameters specifically for their designs.
Even if you run 2700X with LN2 and disable all of the power / current limits, it will not boost higher than e.g. 4.35GHz for the best two cores of the CPU.
4.35GHz for the best two cores of the CPU (marked with a golden and silver star in Ryzen Master), 4.2GHz for the rest (1-2C load).
4.075GHz for all cores, unless limited by PPT, TDC, EDC, thermal or reliability (FIT). Clock reductions starts at 85Â°C (95Â°C tCTL), unless configured to a lower value.
The power management must be reconfigured in order to allow higher frequencies, my "eXFR" ("Performance Enhancer" on ASUS boards) does just that.
The "Precision Boost Override" feature available on 400-series motherboards allows increasing the physical limiters mentioned earlier. On SKUs belonging to the 105W TDP infrastructure group, the default limiters are following: PPT 141.75W, TDC 95A, EDC 140A and tJMax of 85Â°C (absolute, excl. offset).
When "Precision Boost Override" mode is enabled (AGESA default), PPT becomes essentially unrestricted (1000W), TDC is set to 114A and EDC to 168A. These limits can be customized by the ODM so that the new limits will comply with the electrical characteristics of the motherboard design in question.
To see what the actual maximum voltage FIT allows the CPU to run at in various different scenarios is, I disabled all of the other limiters and safe guards. With every other limiter / safe guard disabled, the reliability (FIT) becomes the only restrain. The voltage command which the CPU sends to the VRM regulator via the SVI2 interface and the actual effective voltage were then recorded in various scenarios. In stock configuration the sustained maximum effective voltage during all-core stress allowed by FIT was =< 1.330V. Meanwhile, in single core workloads the sustained maximum was =< 1.425V. When the â€œFITâ€� parameters were adjusted by increasing the scalar value from the default 1x to the maximum allowed value of 10x, the maximum all-core voltage became 1.380V, while the maximum single core voltage increased to 1.480V. The recorded figures appear to fall very well in line with the seen and known behavior, frequency, power and thermal scaling wise.
The seen behaviour suggests that the full silicon reliability can be maintained up to around 1.330V in all-core workloads (i.e. high current) and up to 1.425V in single core workloads (i.e. low current). Use of higher voltages is definitely possible (as FIT will allow up to 1.380V / 1.480V when scalar is increased by 10x), but it more than likely results in reduced silicon lifetime / reliability. By how much? Only the good folks at AMD who have access to the simulation data will know for sure.
There are clear differences in how the memory controller behaves on the different CPU specimens. The majority of the CPUs will do 3466MHz or higher at 1.050V SoC voltage, however the difference lies in how the different specimens react to the voltage. Some of the specimens seem scale with the increased SoC voltage, while the others simply refuse to scale at all or in some cases even illustrate negative scaling. All of the tested samples illustrated negative scaling (i.e. more errors or failures to train) when higher than 1.150V SoC was used. In all cases the maximum memory frequency was achieved at =< 1.100V SoC voltage.